24
Step 3 is similar to step 1, where the bus master
sets the node 02 DHC controller's PACS
®
Command Input to 30.90% ($0C12) followed by
a read of the PACS
®
Control Register.
Step 4 repeats the broadcast LEVEL command to
reset the PACS
®
timers for another 2 seconds.
Since the DHC controllers are required not
to
respond to the broadcast commands in step 2 and step 4, the
bus master will need to wait a sufficient amount of time
before accessing the next node to insure that it is ready.
Without a response, the bus master will need to wait the
200msec maximum response time; this effectively reduces
the time allowed for the next step to 1.8 seconds. The
broadcast LEVEL command could also be sent after every
other node access, or after every three node accesses, or at
whatever interval comfortably sends the broadcast
command within 2 seconds. Naturally, it will be desirable
to access other parameters. So step 1 and step 3 could
include access of such parameters provided that the total
time spent in either step does not exceed the time allowed.
OVERRIDING AN ANALOG COMMAND TYPE
Systems using large numbers of nodes for
controlling various processes may be designed to operate
the DHC controllers with analog signals. In such a system
the Modbus master device might be equipped with a digital
to analog interface which can be updated more rapidly than
sending a serial sequence of PACS
®
Command Input
parameters to a large number of nodes. The digital to
analog interface would provide a constant signal to each of
the DHC controllers, thus eliminating concerns of a PACS
®
timeout. In this type of system, the master device can
"override" the analog command signal by merely setting the
appropriate analog output to any desired value. Therefore,
the bus is only used to monitor various parameters in the
DHC controller, and the PACS
®
Timeout Setting
parameter can be ignored.
Due to the complexities of PID process control
loops, it might not be practical for the Modbus master
device to handle a large number of nodes. In this instance,
it is likely that dedicated PID control devices, which might
even be nodes on the bus, are used instead. In this type of
system, a PID controller provides an analog command
signal to a DHC controller associated with the process.
The bus master can override an analog command
signal that comes from a dedicated PID controller by setting
bit 0 of the PACS
®
Control Register parameter to "1".
While bit 0 is "1", the DHC controller will use the PACS
®
Command Input value instead of the analog command
signal to control the actuator position. However, before bit
0 can be set, the PACS
®
Timeout Setting parameter must
be set to a non-zero value since bit 0 is cleared to "0" when
a timeout occurs.
A system that intends to use the bus to override
analog signals will need to initialize the DHC controller in a
similar manner as described in USING A DIGITAL
COMMAND TYPE. The initialization sequence in this
case does not need to write the PACS
®
Command Input
value since this will probably be done at the time an
override operation is performed.
Consider a system that uses the following
initialization sequence:
1. PACS
®
Command (ORS#ED,#80) 6A 00 ED 80
2. PACS
®
Command (CS#EE,40) 62 00 EE 28
Step 1 sets bit 7 of the PACS
®
Control Register parameter
to "1" to allow monitoring for a power loss. Note that bit 0
is left at "0"; this will be set to "1" when an override
operation is performed. Step 2 sets the PACS
®
Timeout
Setting parameter to 20 seconds (40 decimal, or 28
hexadecimal, times 0.5 seconds).
During normal operation, the bus will only
monitor, or read, parameters. When the bus detects a
situation that requires overriding the DHC controller's
analog command input, a desired position value will be
written to the PACS
®
Command Input parameter first,
then bit 0 of the PACS
®
Control Register parameter will
be set to "1". The following example shows a series of
commands that illustrate a possible override operation
addressed to the node 01 DHC controller. The CRC/LRC
bytes are not shown.
Step Requesting ADU Responding ADU
1 01 41 50 00 ED 01 41 80
01 41 51 00 B8 01 41 0D 22
2 01 41 50 00 ED 01 41 80
01 41 51 00 B8 01 41 0D 3D
3 01 41 82 00 D8 03 E8 01 41
01 41 6A 00 ED 01 01 41
4 01 41 50 00 ED 01 41 81
01 41 51 00 B8 01 41 03 EB
5 01 41 68 FE 01 41
6 01 41 50 00 ED 01 41 80
01 41 51 00 B8 01 41 0D 01
In steps 1 and 2, the first line shows the bus
monitoring the PACS
®
Control Register parameter to
check for power loss. Since the bit 7 of the returned value,
$80 (1000 0000 binary), is "1", the bus continues normal
operation. Had bit 7 been "0", then the next line would
have started an initialization sequence. The second line
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