Philips 40PFL7605H/12 - Page 58

Circuit Descriptions
EN 58 Q552.1E LA7.
2010-Feb-19
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Figure 7-25 TCON architecture
For the TCON block diagram, refer to figure 7-26 TCON block
diagram.
Figure 7-26 TCON block diagram
18770_238_100127.eps
100127
EEPROM
TFT – LCD Panel
Mini - LVDS
Control
Signals
+3.3 V
+1.8 V
V
GH
(+28 V)
V
GL
(-6 V)
+12 V
LVDS
(10 bit)
Timing
Controller
Power
Block
Gamma
Reference
Voltage
Source Drive IC
Gate Drive IC
PNX8550
LCD Panel
TCONMain Platform
SSB
+16 V
18770_239_100127.eps
100127
LVDS
Receiver
LVDS
Receiver
Vertical & Horizontal
Timing g eneration
Data
Path
Block
(Line
Buffer)
M ini-LVDS
Transmitter
M ini-LVDS
Transmitter
OPC
(Optimum
Power
Control)
(Over
Drive
Circuit)
(Dynamic
Contrast
Control)
ODC DCA
Form atter/S erializer
S pread
S pectrum
S DRAM
I
2
C
Slave
I
2
C
Master
ROM
EEPROM
16 bit
H
sync
/
V
sync
DE
SS
CLK
(S pread Spectrum C lo ck)
RLV P /N
Right h alf
data
Gate Driver
Ctrl S ig nals
Source D rive r
Ctrl S ig nals
R1A~E
R1CLK
R2CLK
R2A~E
Mini-
LVDS
Output
LVDS
Input
Control
Signal
Output
Timing Controller IC