Description
of
signal
names
Signal name Signal flow Function
128Fs SBC
-->
n.C.
clock
256Fs SBC
.....
DAI system clock
SBC
-->
SBF
SBC
-->
ADC
SBC
-->
DAC
SBC
-->
ADAS
Explanation
Clock output from SBC, 128 x sampling frequency.
Master clock signal (256 x sampling frequency) for SBF,
DAI, ADC, DAC and ADAS.
Is
generated by SBC with
exception of the mode Digital Record.
In
that case the
DAI
is the MASTER and supplies 256Fs on MSTCK pin. See
also MSTCK.
Fs=32 kHz for DAB, DSR or
BS
(digital audio broadcast).
Fs
=
44.1
kHz for
CD
and DCC.
Fs=48 kHz for professional recording and OAT.
ADRSO
ADRS1
ADRS2
ADRS3
ADRS4
ADRS5
ADRS6
ADRS7
ADSDI
ADSEL
ANA L
ANA R
ASL
An
AnDAC
AUX
AUXENV
AZCHK
BIASA
BIASD
CAP A
CAP B
CAPSTAN
CASN
CHO
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CHROME
DDSP
-->
DRAM
ADC
-->
DAI
DAI
-->
gnd
read amp
-->
analog Pb
equalization
DAI
-->
+5V
SBC
-->
DAC
SBC
-->
DAC
DEQ
-->
DDSP
DEQ
-->
Main IlP
DDSP
-->
test pin
DEQ
-->
high
DEQ
-->
low
Capstan motor
-->
speed
control
Main IlP
-->
7359
DDSP
-->
DRAM
DEQ
-->
DDSP
RE
Deck electronic
-->
Analog
Pb
equalization
address lines
analog/digital serial
data input
control line
signal line
control line
attenuation
attenuate DAC
auxiliary channel
output
auxiliary envelope
azimuth check
control line
control line
control line
control line
control line
channel n
control line
15
8 address lines
to
DRAM to locate
an
address for writing
data into or reading data from memory.
DAI input for serial data from AD convertor (see also S-
DATA).
Serial data output source selection
Analog signal left (right) channel playback analog compact
cassette.
Audio sample length selection
Data input for DAC to set his attenuation register.
Control line (output from SBG) connected to DAC
attenuation input.
Sliced output from DEQ of auxiliary channel data (bit rate
12 kb/s) routed to DDSP input TAUX.
_Digital representation of the AUX signal and monitors
during DCC search mode the start of a track.
Monitors the azimuth of channels 0 and 7 (output of
DDSP).
Bias current for internal AID converter of DEQ2
Bias current for internal AID converter of DEQ2
Via connection points A and B of capstan motor the
reference of the integrated speed control is controlled by
the additional external speed control.
Low output level switches the capstan motor on.
Column address strobe for DRAM
DEQ channel n output
to
DDSP inputs
TCHO
..TCH7.
Indication if a chrome analog cassette
is
inserted. Chrome
Cassette is high level.
CS45915
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