SM5907AF – COMPRESSION-TYPE ANTI-SHOCK MEMORY CONTROLLER NPC
Pin Name Direction Description
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1 VDD2 +2.6V supply voltage
2 UC1 NPC ↔ µP interface extension I/O line 1
3 UC2 NPC ↔ µP interface extension I/O line 2
4 UC3 NPC ↔ µP interface extension I/O line 3
5 UC4 NPC ↔ µP interface extension I/O line 4
6 UC5 NPC ↔ µP interface extension I/O line 5
7 NACS3 NPC → DRAM DRAM2 CAS control
8 TEST2 +2.6V test pin
9 CLK CD10 → NPC 16.9344MHz clock input
10 VSS GND ground
11 YSRDATA CD10 → NPC audio serial data input
12 YLRCK CD10 → NPC audio serial L/R clock input
13 YSCK CD10 → NPC audio serial bit clock input
14 ZSCK NPC → CD10 audio serial bit clock output
15 ZLRCK NPC → CD10 audio serial L/R clock output
16 ZSRDATA NPC → CD10 audio serial data output
17 YFLAG CD10 → NPC signal processor IC RAM overflow flag
18 YFCLK GND crystal-controlled frame clock input
19 YBLKCK CD10 → NPC subcode block clock signal output
20 RESET µP → NPC system reset input (active low)
21 ZSENSE NPC → µP interface status output
22 VDD1 +2.6V supply voltage
23 YDMUTE → NPC forced mute input
24 YMLD µP → NPC µP interface latch clock input
25 YMDATA µP → NPC µP interface serial data input
26 YMCLK µP → NPC µP interface shift clock input
27 A10/NCAS2 NPC → DRAM DRAM OE control output (active low)
28 CAS NPC → DRAM DRAM CAS control output (active low)
29 D2 NPC ↔ DRAM DRAM data input/output 2
30 D3 NPC ↔ DRAM DRAM data input/output 3
31 D0 NPC ↔ DRAM DRAM data input/output 0
32 D1 NPC ↔ DRAM DRAM data input/output 1
33 WE NPC → DRAM DRAM WE control output (active low)
34 RAS NPC → DRAM DRAM RAS control output (active low)
35 A9 NPC → DRAM DRAM address output 9
36 A8 NPC → DRAM DRAM address output 8
37 A7 NPC → DRAM DRAM address output 7
38 A6 NPC → DRAM DRAM address output 6
39 A5 NPC → DRAM DRAM address output 5
40 A4 NPC → DRAM DRAM address output 4
41 A0 NPC → DRAM DRAM address output 0
42 A1 NPC → DRAM DRAM address output 1
43 A2 NPC → DRAM DRAM address output 2
44 A3 NPC → DRAM DRAM address output 3
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