Philips CD721 - Page 26

3.4. Functional description
3.4.1. Front-end
Data slicer
The SAA7345 has an integrated slice level comparator
which is clocked by the crystal frequency clock.
2nZg
HPI 2Ka
22K
ale
ISLICE
330n
ac
Digital PLL
Regeneration of the bit clock is achieved with an internal
fully digital PLL. No external components are required
and the bit clock is not output. The PLL has two micro-
processor control registers(addresses 1000 and 1001) for
bandwidth and equalization.
Error corrector
The error corrector carries out t=2, e=0 error corrections
on both C1(32 symbol) and C2(28 symbol) frames. Four
symbols are used from each frame as parity symbols.
The strategy t=2, e=O0 means that the error corrector can
correct two erroneous symbols per frame and detect all
erroneous frames.
The error corrector also contains a flag processor. Flags
are assigned to symbols when the error corrector cannot
ascertain if the symbols are definitely good. C1 generates
output flags which are read {after de-interleving) by C2,
to help in the generation of C2 output flags.
3-3
The slice level is controlled by an internal current source
applied to an external capacitor under the. control of the
digital phase-locked loop(DPLL).
CRYSTAL CLOCK
An offtrack input(OTD) is input via the Vipin (pin3) of
the
versatile
pins-interface.
When
this
flag
is
HIGH,
the
SAA7345 ‘will assume that the servo -is following on the
wrong
track,
and
will
flag
all
incoming
HF
data
as
incor-
rect.
The
C2
output
flags
are
used
by
the
interpolator
for
concealment
of
uncorrectable
errors.
They
are
also
out-
put
via
the
EBU
signal(DOBM)
and
the
MISC
output
with
i?S
for
CD-ROM
applications.
The flags output pin CFLG provides infomation on the
State of all error correction and concealment flags.
in
comparison
with
CD4+,
CD6
has
a
bettw-
error
correc-
tor.
The
error
correction
performance
of
ClG
depends
on
which
crystal
is
used
and
on
which
speec
is
performed.
The
best
performance
is
achieved with a 33.9 MHz crystal at single 5 peed.
PCS 60.959