Philips CDR930 - Page 77

Electrical diagrams and PWB’s
GB 53CDR 3rd gen. 7.
3909 E5
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A
B
C
D
E
F
A
B
C
D
E
F
1812-1 C4
1818 E3
1819 E4
1820 A1
1830-1 A4
1831 B7
2600 A6
2601 A8
2603 B6
2604 C8
2605 C6
2606 C6
3900 B1
3901 B1
3902 D1
3904 C1
3905 E1
3907 E5
3908 E5
2600
10n
2605
10n
10n
2603
GND_CASE
3
4
5
6
7
2
4
1818
PH-B
1
2
6
10n
2601
2
8
3907
4K7
1K
3908 3909
4K7
3104 123 4228.7
1812-1
52207 1
11
10
3
GND_CASE
GND_CASE
0R
3902
GND_CASE
GND_CASE
5
9
0R3900
1830-1
1
GND_CASE
3905
100R
GND_CASE
1831
3
4
5
6
7
8
9
100R
3904
18
19
2
20
21
22
23
24
25
26
27
28
29
3
30
1820
1
10
11
12
13
14
15
16
17
7
4
9
2604
10n
1819
PH-B
1
2
3
4
5
6
7
8
10n
2606
3901 0R
SGND
{BKPT,DSCLK,DSI,HDCD,LEVEL_A0,LEVEL_A1,LEVEL_A2,RXD_TOOL,TXD_TOOL,TCK,TRACE99_RxD,TRACE99_TxD,TDSO}
INT_COPY_ANA
DSA_COPY
DSA_DATA_CD
{EXT_DIG_IN,DIG_OUT_C,EXT_OPT_IN,DISPL_INT,SYS_RESET,DSA_DATA_CD,DSA_ACK_CD,DSA_STR_CD,KEY_PRESSED,IIS_DATA_CD,IIS_WS_CD,IIS_BCLK_CD,DOBM_CD,SYS_CLK_8W,DIG_IN2,KILL}
IIS_DATA_CD
LEVEL_A2
{SEL_HP_OUT,INT_COPY_ANA,SYS_CLK_11B,L3_MODE,IIS_BCLK_A0,IIS_WS_A0,IIS_DATA_A0,IIS_BCLK_A1,IIS_WS_A1,IIS_DATA_A1,L3_DATA,L3_CLK,NMUTE,PROF_EBU}
BKPT
DSCLK
DSI
TDSO
TCK
CLK_OUT
CLK_OUT
RESET_MIN
WRITE_TOGGLE
D3V3 D3V3
TERMB
TERMB
TRACE99_TxD
TRACE99_RxD
D5V
TXD_TOOL
RXD_TOOL
KILL
PROF_EBU
EXT_DIG_IN
DIG_IN2
DIG_OUT_C
EXT_OPT_IN
IIS_WS_A0
IIS_BCLK_A0
IIS_DATA_A0
IIS_WS_A1
DSA_DATA_CDR
DSA_ACK_CDR
DSA_STR_CDR
{DSA_ACK_CDR,BE_RESET,DSA_STR_CDR,DSA_DATA_CDR,MUTE,ATT,DEEMP,IIS1_MS,SYS_CLK_BE}
D5V
SYS_RESET
SEL_HP_OUT
CDR60CL1
PCSSIN
PCSCOS
CDR60CFLG
CDR60MEAS1
MERR
MERRIN
HALL_U
HALL_V
HALL_W
{CDR60MEAS1,CDR60CFLG,CDR60CL1,MERR,MERRIN,HALL_V,HALL_U,HALL_W}
{REFSIN,REFCOS,PCSSIN,PCSCOS}
IIS_BCLK_A1
IIS_DATA_A1
HDCD
LEVEL_A0
LEVEL_A1
NMUTE
L3_MODE
CL06532018_053.eps
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