Electrical diagrams and PWB’s
GB 55CDR 3rd gen. 7.
D
E
F
123
2710 C10
2711 C10
2715 C5
2720 H9
3011 H10
3754 H7
4567891011
F980 F9
F981 F9
OPTION
4
3759 I7
3780 I10
7708-B G7
7708-C H10
7708-D H7
7999 G12
F754 B4
F755 B10
F902 H7
F904 I7
C
3898-D G12
3999 G12
5712 B9
5713 C4
5716 G7
7702 C3
7703 C9
7705-A G11
7708-A G8
A
B
F
G
H
I
2700 C5
2701 C5
2702 C5
2705 G7
OPTION
1
G
H
I
A
B
C
D
E
F947 E10
F950 H11
1223
5 6 7 8 9 10 11 12
3817 E10
3841 H11
3842 I11
1
2
7
14
3
F754
74HC00D
7708-A
F902
7708-B
74HC00D
4
5
7
14
6
2700
100n
BLM21
5712
1K
3759
2701
100u
100K
3780
2
1
8
4
MC34072
7705-A
3
37
VSS1
27
VSS2
46
WE_
11
7999
BC848B
43
DQ15|A-1
45
DQ2
33
DQ3
35
DQ4
38
DQ5
40
DQ6
42
DQ7
44
DQ8
30
DQ9
32
NC2
10
NC3
13
NC4
14
OE_
28
RESET_
12
RY|BY_
15
VCC
23
A3
22
A4
21
A5
20
A6
19
A7
18
A8
8
A9
7
BYTE_
47
CE_
26
DQ0
29
DQ1
31
DQ10
34
DQ11
36
DQ12
39
DQ13
41
DQ14
7703
A0
25
A1
24
A10
6
A11
5
A12
4
A13
3
A14
2
A15
1
A16
48
A17
17
A18
16
A19
9
A2
F755
Am29LV160BB
74HC00D
7708-C
9
10
7
14
8
F980
7708-D
74HC00D
12
13
7
14
11
82R
3011
3999
0R
F904
1K
3817
100n
2715
2705
100n
F950
1n
2720
47R
3898-D
F947
3842
0R
0R
3841
F981
2710
100u
BLM21
5716
3104 123 4228.7
5713
BLM21
2702
100n
21
VCC3
22
VSS1
37
VSS2
42
VSS3
13
WE_
I|O3
7
I|O4
8
I|O5
9
I|O6
10
I|O7
33
I|O8
34
I|O9
31
LCAS_
11
NC1
12
NC2
32
NC3
29
OE_
14
RAS_
30
UCAS_
1
VCC1
6
VCC2
A3
23
A4
24
A5
25
A6
26
A7
27
A8
28
A9
2
I|O0
3
I|O1
I|O10
35
36
I|O11
38
I|O12
39
I|O13
40
I|O14
41
I|O15
4
I|O2
5
GM71C18163CJ-6
7702
17
A0
18
A1
16
A10
15
A11
19
A2
20
100n
2711
D3V3
{RAS0,CAS0,CAS1,DRAW_RW,F_READY,CSFLASH,F_RW,RESET_MIN}
+12VX
V7708
D(16:31)
SYS_CLK_IIW
SYS_CLK_11B
1K
3754
D(30)
D(31)
F_RW
D3V3
D3V3
F_READY
D3V3
A(19)
A(20)
RESET_MIN
A(11)
A(12)
A(13)
A(14)
A(15)
A(16)
A(17)
A(18)
V7708
V7708
WRITE_TOGGLE
D3V3
V7708
V7708
A(15)
A(16)
A(17)
A(18)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
A(10)
CSFLASH
A(1:20)
D(16)
D(17)
D(18)
D(19)
D(20)
D(21)
D(22)
D(23)
D(24)
D(25)
D(26)
D(27)
D(28)
D(29)
A(10)
A(20)
D(16)
D(17)
D(26)
D(27)
D(28)
D(29)
D(30)
D(31)
D(18)
D(19)
D(20)
D(21)
D(22)
D(23)
D(24)
D(25)
CAS1
RAS0
CAS0
DRAW_RW
A(1)
A(2)
A(11)
A(12)
A(13)
A(14)
R7
CDR MAIN BOARD - CIRCUIT DIAGRAM 10 : DASP FLASH & DRAM TESTPOINTS
CL06532018_055.eps
290200
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