TMS320DA150PGE160 – DIGITAL SIGNAL PROCESSOR DSP
Pin Name Direction Description
–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
1 CVSS1 GND ground for core CPU
2 A22 DSP ↔ parallel address bus
3 CVSS2 GND ground for core CPU
4 DVDD1 +3.3V power supply for I/O pins
5 A10 DSP ↔ parallel address bus
6 HD7 CD10 → reference current output pin
7 A11 DSP ↔ parallel address bus
8 A12 DSP ↔ parallel address bus
9 A13 DSP ↔ parallel address bus
10 A14 DSP ↔ parallel address bus
11 A15 DSP ↔ parallel address bus
12 CVDD1 +3.3V power supply for core CPU
13 HAS → DSP address strobe input
14 DVSS1 GND ground for I/O pins
15 CVSS3 GND ground for core CPU
16 CVDD2 +core power supply for core CPU
17 HCS → DSP chip select input
18 HR/W → DSP read/write input
19 READY → DSP data ready input, indicates that an external device is prepared for a bus
transaction to be completed
20 PS DSP → EPROM program space select output, always high unless driven low for
communicating to a particular external space
21 DS DSP → data space select output, always high unless driven low for communicating
to a particular external space
22 IS DSP → I/O space select output, always high unless driven low for communicating to
a particular external space
23 R/W DSP → DRAM read/write signal output, indicates transfer direction during communication to
an external device
24 MSTRB DSP → memory strobe signal output
25 IOSTRB DSP → I/O strobe signal output
26 MSC DSP → microstate complete output, indicates completion of all software wait states
27 XF DSP → external flag output, latched software programmable signal
28 HOLDA DSP → Hold acknowledge, indicates that the processor is in a hold state
29 IAQ DSP → instruction acquisition signal output
30 HOLD → DSP hold input, asserted to request control of address, data and control lines
31 BIO → DSP branch control input
32 MP/MC → DSP microprocessor/microcomputer mode select
33 DVDD2 +3.3V power supply for I/O pins
34 CVSS4 GND ground for core CPU
35 BDR1 CD10 → DSP serial data receive input
36 BFSR1 CD10 → DSP frame synchronization pulse for receive input
37 CVSS5 GND ground for core CPU
38 BCLKR1 CD10 → DSP serial shift clock
39 HCNTL0 → DSP control input
40 DVSS2 GND ground for I/O pins
41 BCLKR0 CD10 → DSP serial shift clock
42 BCLKR2 µP → DSP serial shift clock
43 BFSR0 → DSP frame synchronization pulse for receive input
44 BFSR2 → DSP frame synchronization pulse for receive input
45 BDR0 → DSP serial data receive input
46 HCNTL1 → DSP control input
47 BDR2 µP → DSP serial data receive input
48 BCLKX0 DSP → CD10 transmit clock
49 BCLKX2 µP → CD10 transmit clock
50 CVSS6 GND ground for core CPU
51 HINT DSP → interrupt output, used to interrupt the host
52 CVDD3 +core power supply for core CPU
53 BFSX0 DSP → CD10 frame synchronization pulse for transmit input/output
54 BFSX2 µP → DSP frame synchronization pulse for transmit input/output
55 HRDY DSP → ready output, informs the host when the HPI is ready for the next transfer
56 DVDD3 +3.3V power supply for I/O pins
57 DVSS3 GND ground for I/O pins
58 HD0 DSP ↔ parallel bidirectional data bus
59 BDX0 DSP → CD10 serial data transmit output
60 BDX2 DSP → µP serial data transmit output
61 IACK DSP → interrupt acknowledge signal output
62 HBIL → DSP byte identification, identifies the first or second byte of transfer
63 NMI → DSP nonmaskable interrupt input
64 INT0 → DSP external user interrupt input
65 INT1 → DSP external user interrupt input
66 INT2 → DSP external user interrupt input
67 INT3 → DSP external user interrupt input
68 CVDD4 +core power supply for core CPU
69 HD1 DSP ↔ parallel bidirectional data bus
3-4
To Next Page
Loading...
