Philips PM 3266 - Page 111

116
3.2.4.
1.
Delayed
time-base
trigger
source selector
and
preamplifier
The
signal
which
is
applied
to the
external
trigger
input
X6 is
fed via
the
input stage
consisting
of FET
transistor
V1
101 and
integrated
circuit
D1
101
to
the
base of V1
104,
When
DC
coupling
is
selected with
switch
SI
9,
a
DC
path is
formed via
the
resistors
R
1 1 03 and
R 1 1 04
to
input
3 of D1
101
.
In the LF
and HF
mode
the DC
path
is blocked.
The
l.f.
component
of
the signal
is fed
via
capacitor
Cl
102
to point
3
of
D1
101 and
the h.f.
component
is then fed
via
capacitor
Cl
101
to
FET
transistor
V1
1 01
. The output
signal
from
V1
1
01 and D
1 1 01 is
then
applied
to the
base of
transistor
VII
04.
In
the
modes
A, B and
MTB
the
emitter
of
transistor
V1
102 is
connected
to the
+11,4
V via
switch
S21,
transistor
V1 102
is
conducting
thus
blocking
the
signal
path via
the diode
V1
103.
When
mode EXT
is selected,
there
is no
voltage
applied
via
S21
to the emitter
of
transistor
V1 102. This
transistor
is
blocked
and the
signal
path via
diode
V1 103
is
opened.
The
gain
of the
low
frequency
path is
set
by adjusting
the
resistor
divider
ratio from
which
the
output
is
sampled.
Adjusting
is
done
with
preset
potentiometer
R1118
(L.F.
corr.).
3.2.4.
2. Delayed
time-base
trigger
amplifier
The
delayed
time-base
trigger
amplifier
consists
of
an input
stage,
coupling
filters
and
a final
amplifier.
The
signal
current
from
the
intermediate
amplifier
(channel
A,
channel
B or
composite)
is fed
via
the
trigger
source
selector
circuit
to the
emitter
of
VI
203. The
output from
the
trigger
source
(EXT)
is
also
fed
to the
emitter
of
VI
203.
This
transistor
connected
in
common-base
configuration,
is coupled
to the
shunt
feed-back
stage
VI
204,
VI
206.
The
output
of
this
stage is
diode-coupled
to the
filters
for
the various
coupling
modes.
By
means
of
these
filters,
the
input
frequency
range of
the
trigger
circuit
can be
set.
The
desired
filter
is
switched
in
by biasing
the
appropriate
switching
diodes
in
the
forward
direction
via two
resistors.
For
example,
the
DC
position,
selected
by
switch
SI
9,
is switched
in by
the
-1
1
,4 V
which
causes
diodes VI
208 and
VI
21
2 to conduct.
The
LF
and
HF
modes
are selected in
a similar
way.
The
filter
section
is
coupled
to an
emitter-follower
VI
214,
which
compensates
for
the
temperature
drift of
transistor
VI
204.
The two
transistors VI
21
6
and
VI
21
7
accept
the trigger
signal
and the
trigger
LEVEL
voltage
respectively.
The LEVEL
voltage
control R5
permits
variation
of the
trigger
level of
the
signal.
The
collector
currents
of
VI
21 6 and VI
217 are fed
to
the
shunt
feedback
stage VI
219 and VI
218
respectively,
thus
providing
the trigger
signal.
In the
negative
position
of the
+/—
SLOPE
switch
S6, the trigger
signal is
taken
from
one
of the collectors
via
V1224
and
diode
V1223,
and in
the
positive
position
via V1221
and diode
V1222.
+/-
SLOPE
switch
S6 determines
the
polarity of
the trigger
signal. In
the closed
position
a 0 V signal
causes
VI
223 to conduct
the negative
trigger,
and
also switches
off
VI 228. In
the open
position,
VI 228
is switched
on and the
positive
trigger
is routed
via VI
222
and VI 223 is
blocked.
In
this
way the
appropriate
trigger
signal is
supplied
to the
time-base.