132
The first
section of
the
timer
provides
the 100
ms pulse on D221
1-10
immediately after
the
release of the
ERASE
pushbutton.
This pulse is
routed
via diode V2226 and R2486
to the
emitter
of
transistor
V2458 at
the input of the
front mesh amplifier.
As
described in the WRITE
mode, this positive-going
100
ms pulse
is
fed
to the
base of V2431,
which conducts
and
cuts
off series
transistors
V2426, V2427.
Transistors
V2421,
V2422
conduct the 500 V
first erase
pulse and apply
it
to
the front
mesh.
At the
end of the TOO ms
pulse
the potential of the front
mesh reverts for
500 ms to
approximately
0 V, the
potential at the
output of the front
mesh
preamplifier.
Also at the time
t^, the 600 ms
pulse
on output D221
1-11
is routed
to inputs
5
and 1
2 of the
quadruple
bilateral
switches
D2401. These switches
control
the inputs to the flood
gun accelerator
amplifier and
the
collimator 1
amplifier.
The positive-going
pulse on control input D2401-5
switches
the 0 V on pin 4 to
pin 3. The resulting
drop
in potential at the
base of V2437
causes the output
transistor
V2439 to conduct further,
and the flood gun
accelerator
potential on R2504 is
raised from
-^20
V to
^50
V for the
duration
of the 600 ms pulse.
At t(j,
the positive
pulse on control input
D2401-12
applies the 0 V on pin 1
1
via
pin 10 and
R2403 to
the
base
of
V2444,
the input
of
the
collimator
1
amplifier. Transistor
switches
off and the increase
in its
collector
potential
causes
a
further
conduction
of output transistor
V2446. The collimator
1
potential increases
from
-h
30 V to
-1-90
V
as
a
result, for
the duration of
the 600 ms
pulse.
At the end
of
the
600 ms pulse,
collimator
3
is
raised from 75
V to
a
value
between
+75
V and
+100
V,
adjustable by R2404,
by a
logic
1 on
the Q output
of flip-flop D2229 {FAST
input
on D and
a clock pulse
from
D2226-10 after
600
ms). This logic 1
is routed via diode
V2233 to control
input
D2401-13.
This applies
the 0 V on
pin 1
to the input of the
collimator
3 amplifier, V2449,
V2451
.
The
second
erase
pulse is generated
after
tg
+600
ms and holds
the front
mesh at
approximately +10
V
for
900 ms. It is
provided
by the 1
500 ms
timing pulse derived from
AND
gate output
D221 1-3,
which feeds a
logic 1 to
AND
gate
input D2224-13.
Input 12
is also
at logic
1 in the FAST
mode
and input 11
is at logic 1
at the end
of the 600
ms pulse,
therefore
output D2224-10
is at logic 1.
This signal
is
fed
to
the control
input of D2402-1
2,
which connects
the
+1
1 .2 V input on
pin 1
0 to pin 11.
The resulting +10
V
second erase
voltage
is
set by preset control R2429.
At the end of
the
second erase pulse
the
front mesh
potential
is lowered slightly
to approximately
0
V
until
the
transfer pulse
at the
end of the
time-base
sweep. This
potential
is initiated by
the
positive-going
SET
FRONT MESH
input
pulse
to D2403-6,
derived from
the
Q output of
the D2216
flip-flop
at t^
+
1500
ms.
This input
logic
1 on D2403-6
switches
the
+1
1.2
V
on
pin 9
to pin
8,
thereby
increasing
the
input potential
of
the front
mesh preamplifier
slightly, thus
reducing
the output
potential from +10
V to 0
V.
Preset
R2419
on the
preamplifier
input
permits
adjustment
of this voltage.
Fast Mesh
During
the preparation
of
the front
mesh,
the fast
mesh potential
is lowered from
+140
V to
+5
V at
300 ms
after
the
start of the
second
erase pulse,
i.e. at
tQ
+900
ms. This is
achieved by
a positive
pulse
from flip-flop
D2216
on output
pin 1.
The clock
input
of this flip-flop
is derived from
the
900
fVis output of
D2214-1
1.
The
Q output from
D2216
is routed
via R2246
to an oscillator
formed
by timing
capacitor
C2228 and
the
complementary
transistors
V2243,
V2244 (the
stabilisation
pulse generator).
This
provides
150 Hz
pulses
with
a
duty
cycle
of
0.07 %
at input 1
2 of AND
gate
D2231
.
Input
13 of
D2231 is
als^at logic 1
for the period
of
t^
+
900 ms until
the end
of the time-base
sweep. This
pulse
is
derived
from the
Q output
of
flip-flop D2216-2 which
together with
the Q
output of D2216-12 is fed
via AND
gate D2209-10
and inverter D2228/3,2
to input D2231-13
as
a
logic
1.
The
pulses
on
output
D2231-1
1 are routed
via diode
V2230 to control
input 6 of transmission
gate D2402.
By this
means, pulses
are switched
at 1 50 Hz from
input
9
(+1 1 .2 V)
via output
8 to the base of
V2402
at the input
of the fast
mesh amplifier.
The
low level
of the input
pulses
is adjusted by preset R2408.
Transistor
V2402
conducts
on
the negative-going
pulses, which
results
in
negative-going
pulses
at the collector
of V2403.
These are
inverted by V2408
and applied
to the
bases of the
complementary
output transistors
V2404,
V2407. The
output on
the junction
of
the emitters
consists of
the fast
mesh preparatory
pulses
at a frequency
of
150
Hz,
positive-going from
about +5
V to
+140
V
(duty
cycle 0.07
%).
The
pulses are present
until
the begin
of the
time-base
sweep.
Time-base
The
time-base
is unblocked
at a time of
100
ms
following
the
end of
the second
erase
pulse; i.e. at
to
+
1600
ms.
This
is achieved
by
the Q output
of D2216-13
applied to
input
6
of NAND
gate D2203
at 1 500
ms. Together
with
the FAST
input
on pin
5,
this gives
a logic
0 on D2203-4,
which
via
V2263
lowers the input
of the 100
ms
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