Philips VE8 - Page 59

Circuit Diagrams and PWB Layouts
59Q529.1A LA 7.
SSB: STi7100: Debug
V+
V-
VCC
C1+
C1-
C2+
T2
T1
IN
IN OUT
OUT
GND
T1
C2-
R2
R1
T2
R1
R2
A
B
C
D
E
A
B
C
D
E
1AM0 B6
1AM2 D6
2AM0 A4
2AM1 A3
2AM2 A5
2AM3 B5
7AM0 A4
7AM1-1 C4
7AM1-2 E4
9AM0 D5
9AM1 C3
9AM2 E4
FAM0 B5
ST40 DEBUG LINK
STI7100: DEBUG
FAM9 E5
FAMA E5
FAMB E5
FAME E6
FAMJ D5
UART2
7
7
123 456
2AM4 B3
3AM0 D5
3AM1 B3
3AM2 B5
3AM3 B5
3AM7 C4
3AM8 E4
FAM2 B6
FAM3 D5
FAM4 D5
FAM5 D5
FAM6 D5
FAM7 D5
FAM8 D5
UART
123 456
FAM1 B5
10K
3AM8
3AM0
33R
7
8
9
FAM4
17
18
19
2
20
3
4
5
6
1AM2
1
10
11
12
13
14
15
16
5-147279-5
3AM2
100R
10K
3AM7
FAM3
+3V3
FAM2
2AM4
100n
2AM3
100n
FAME
FAMB
FAM7
FAM5
3
714
4
FAM6
714
2
74LVC07APW
7AM1-2
74LVC07APW
7AM1-1
1
100R
3AM3
FAM1
9AM2
FAM0
+3V3
+3V3
7
2
6
16
2AM2
100n
4
5
15
13 12
8 9
11 14
10
Φ
RS232
ST3232C
7AM0
1
3
9AM1
FAMA
3AM1
100R
2AM0
100n
+3V3
FAM8
FAM9
100n
2AM1
9AM0
RES
1
2
3
45
1AM0
B3B-PH-SM4-TBT(LF)
+3V3
FAMJ
JTAG-TDI-ST
JTAG-TDO-ST
RST-TARGETn
JTAG-TRSTn-ST
TRIG-OUT
TRIG-IN
JTAG-TMS-ST
ASEBRKn
JTAG-TCK-ST
RXD-ASC2
TXD-ASC2
BUF-RST-TARGETn
3139 123 6214.4
I_17660_012.eps
110308
B03F
B03F