Radio Shack TRS-80 Model 100 - Page 59

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mffr, (Eiii
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or,
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OOUT
m/T/mm,
:
UNKNOWN
Noie:
(1!
R/W
is
high for
a
Read
Cycle.
(2)
twP
is specified as
the
logical "ANO'jjr C£_l_. CE2
and
R/W.
twp
is measured (rom
lhe latter
of
CH
t.
CE2
or
R/W
going low
to
the
earlier
of
CE
1
.
CE2
or
R/W going
high.
!3)
'OH.
IDS
are measured
(rum
trie earlier
ol CS 1.CE2
or
R/W going
high.
(4)
If
lha
CE~i, or CE2
low
transition occurs
simultaneously
with
or
latter from
the R/W low tran-
sition in
a
Write Cycle
1
.
the output
bulfers
remain in
a
high impedance
state
in
this period.
(5)
If the CE~i or
CE2
high transition
occurs
prior
to
or
simultaneously
with the
R/W high transition
in
a
Write
Cycle 1. the
output buffers
remain
in
a
high
impedance state
in this period.
(6!
If
the
R/W
is low or
the
R/W
low
transition occurs
prior
to
or
simultaneously
with
the
CE
i or
CE2
low transition, the output
Ouflers remain
in
a
highjmpedance state
in this period.
(7)
A write occurs during the
overlap ot a low CE I .
low
CE 2
and
low fl/W.
In
write cycle
2.
write
is
controlled oy
either CEl or CE2.
Fig.
20