Reflex Lexicon - EEPROM Interface and Input Registers

Theory of
Operation
Lexicon
EEPROM 64kbits
(8k
x
8),
24C65
interface
Non-volatile
data storage
is
incorporated
with 2
wire
serial/rC
EEPROM.
This serial EEPROM
(U7)
uses
atwo
wire
bus
protocol.
Pin
5
of
U7
is the serial
address/data input/output.
This is a
bidirectional
pin
used
to
transfer
ad-
dresses and
data
into and
out
of the
device.
Pin
6
of
U7
is the serial clock input
used to
synchronize
the
data
transfer to
and
from
the device.
Output
reg
2
(U5)
bits
5
and
6
are used
to
generate the serial clock and
data
for
the
EEPROM. Input
reg
2
bit
7
is
used to
read the serial
data
from
the
EEPROM.
Software requirements
After
addressing the
EEPROM,
EEPDAI must
remain
in
a
high
logic
state,
so
that
the EEPROM SDA
signal
can
pull
this
signal
to a
low
logic
level
to
generate an
acknowledge
pulse after
the
reception
of
each
byte.
A
note on
the electrical
interface
for
the
EEPROM
data I/O
A
series resistor
(R75)
is
added
between
the
output
data
port of
Output
register 2 and the bidirectional data
port
on the
EEPROM. When trying
to read
from
the
EEPROM,
the
two
outputs
drive
each
other.
As both
devices are
CMOS, no current
will
be
flowing
when
their
outputs
are
at
the same
logic
level,
and the devices
will
not be
driving each other.
If
the
outputs
are
at
different
logic
states,
the
EEPROM
will
be
pulling
its
output up
ordown
during
a
read operation.
When
the
EEPROM
is
not being addressed
it
goes
into
a
standby
mode
where
the data
pin
sits
at a
high logic level.
The
EEPROM interface is
essentially a
programmable Z80 serial
port
which
uses
two bits of
Output
Register 2
for
writing
addresses/data
and
clocking
and
one bit of Input Register 2
to
read data
back.
I/P
Registers
The
two
input
registers
(U4
and U3,
74HC541) are
used
for
reading
front
panel switches
(S2, S4, S5)
and
encoders (S1
and
S3), as
well
as
the
footswitches
(J3
and
J4)
and
EEPROM
serial
data.
It is necessary
to
have
pullup resistors
at
the rotary
encoders
greater
than
31ki2
because the
on
resistance
for
the encoders is
specified to be
less
than
5kQ.
RP2
serves this
function.
RP1
pulls
up the
inputs
to
input
register2,
preventing
U3
inputs
from
floating
and
providing
a
default
non-active switch
state
of logic
high.
Footswitch jacks
J3
and
J4 use
resistors
(R4,
R5)
and
capacitors
(C1 ,
02)
to
filter
out
RFI.
The
follow!
ngtable
defines
Input Register
1 .
Encoders
output
gray scale
code.
Data
Bit
<0:7>
Signal
Name
Active
State
Description
0 SW1-1 0
Value Adjust
encoder
bit
0
(LSB)
1
SW1-2
0
Value Adjust
encoder
bit 1
2
SW1-3 0
Value Adjust
encoder bit
2
3
SW1-4
0
Value Adjust
encoder bit
3
(MSB)
4
SW2-1
0
Register/Preset
Select encoder bit
0
(LSB)
5
SW2-2 0
Register/Preset
Select
encoder bit
1
6 SW2-3
0
Register/Preset
Select encoder
bit
2
7
SW2-4
0
Register/Preset
Select encoder bit
3
(MSB)
4-8