Reflex Lexicon - MIDI I;O Interface and Protocol

Reflex
Service
Manua!
Theory
of Operation
The
followingtable defines Input
Register
2.
Data
Bit
<0:7>
Signal
Marne
Active
State
Description
0 PARAM/ 0
Parameter Select
switch
1
REG-PRE/
0
Register/Preset Select switch
2
STR-CLR/
0 Store
or Clear Register
function
switch
3
FOOT-BYP/ 0
Footswitch Select for Bypass
function
4 FOOT-REG/ 0
Footswitch
Select for
Register Step
function
5 FS2T1P/ 0
not used
6 FS2R!NG/
0 not
used
7
EEP_DAO
0/1
Serial
data
from EEPROM
MIDI
I/O
The MIDI interface
utilized
by
Reflex complies
with
the
MIDI
specification. It
incorporates
5-pin,
female
DIN connectors
for
input and
output (J2
and
J1).
MIDI IN
is opto-coupled
for
ground
isolation through U1 to
the
UART,
U2.The
MIDI
OUT
signal
is
provided
by
the
UART
and
is fed
to
current loop
driver Q1
and
out J1.
FB1 and
FB2 are
used
to
reduce
RFI
radiation.
Jumper
W2
is
provided
for
alternately
configuring
J1
as
a
MIDI THRU jack instead
of
MIDI
OUT
The
Z80 uses
the
UART
as a
peripheral
I/O device and
programs
it
to
communicate
in
an asynchronous
serial
data
protocol.
The
UART
data
available
output
(RxRDY, pin
14)
which signals that the
UART has
received
a
complete character, is
inverted by
section of
the
U1 1
Schmidt
inverter
before being
used to
interrupt the
Z80.
The
UART runs
at
4mHz (ZCLKDLYD/).
This
is
a
dedicated
clock
which
is the
complement
of
ZCLKDLYD. The
spec
states
the clock frequency
must be
more than 4.5 times the
TxCLK or
RxCLK
in async mode
using
x16
clock
mode.
The MIDI
specTransmit
and Receive
Baud rate
=
31.25k.
TxCLK/RxCLK
=
31 .25k
x1
6
=
500kHz. Therefore, the
UART CLK
must
be
greater
than 4.5
x
500kHz
(2.25mHz),
and less
than
8mHz
(max clock
freq for UART).
The TxCLK and RxCLK
is
divided
down
from ZCLKDLYD
with
half
of
a
dual
4-bit
binary
counter
(U11)
to
derive the
500kHz
clock
signal.