Reflex Lexicon - Lexichip II, DRAM, and Clocking; DAC;ADC Control Logic

Theory
of
Operation
Lexicon
Lexichip
II, The Lexichip II
(U14)
performs all
of digital
effects processing
for
the
Reflex.
DRAM,
Clocks
It receives instructions
from
its
internal
program RAM, referred
to as
the
Writeable
Control Store
(WCS).
Address, data,
and
control
lines
forthe
WCS,
as
well
as various Lexichip II control and status
registers
are shared
with
the
Z80
bus.
This
allows
the Z80
to load audio
effects
programs
into
the
Lexichip
II,
monitor
status
of
audio
data,
and synchronously
change
program
parameter
values
in
the audio programs. The Z80
treats
this
memory
as
RAM
mapped
memory
in
its
memory
space
between addresses COOO
and
C307
HEX.
An
internal
crystal
oscillator
driver circuit
drives
a
16MHz crystal
mounted
across
pins
75
and 76
on the
Lexichip
II.
Internal Lexichip II circuitry
divides
this
clock frequency
down
to
provide the
4MHz ZCLK. ZCLK
clock is
reclocked
by a
16MHz
master clock
generated by
the
Lexichip II
using
one
half
of
U13
(74HC74). This
is
to
ensure
setup
and
hold times
for
writing
Lexichip II
WCS.
The
reclocked
ZCLK
(ZCKDLY)
is
also divided
by
four with
one
half
U15
and
used for
the
Baud
clock on
the UART. The
inverted
reclocked
ZCLK(ZCLKDLY/) from LI13,
pin
8
is
used as the
4MHz
UART
clock.
All
clock signals
are conditioned
with 100Q
dampening
resistors. The
same is true
for
Lexichip II
DRAM addresses
and control signals.
Word
Clock
(pin
59)
from
the
Lexichip is
used as
the
clock reference for
Reflex. It
operates
at
31.25kHz rate and
is
the heartbeat of
interrupt timing
circuitry
as explained in
the
Z80
interrupt
timer section.
Audio memory
is configured with
4)
64K X
4bit
DRAMS
(U38,
39, 40,
41
)
with
layout supporting
4)
256K X
4bit or4)
1
M X
4bit
chips
(U20,
21
,
22,
23).
This
provides
the
LEXICHIP with 64K
by
16-bit
memory
for
audio
data storage.
Memory
speeds of 100ns
orfaster are
more
than adequatewhen the
Lexichip
is
running
at
1
6MHz. DRAM
read,
write,
and
refresh
functions
are
performed
by
a
dedicated
set
of
address
and control
lines,
and
a
16-bit
wide
data bus
provided
by
the
LEXICHIP.
DAC/ADC
Control Logic
and Data
Port
Internal
control
logic circuitry
enables the
Lexichip
to
command
complete
control over
external DAC functionality with
minimal
external circuitry.
Two
8-bit latches
(U1 8
and
U19) are used to
latch 1
6-bit
data
out
to
the DAC
via the DAB
(digital audio
bus).
Lexichip
output
CCLK1
clocks
data
into
these
DAC conversion
latches.
An
internal
Successive
Approximation Register
(SAR)
aliows the
DAC, in
conjunction with an
external
comparator, to
perform
analog
to
digital
conver-
sions.
A
data value
is
latched into the
conversion latch,
DAC
output is
compared
to the analog
input
by
the
comparator.
The resulting
output
data
(
DATA)
is
applied
to
Lexichip
input
S1
1 ,
and
the
SAR logic ci rcuitry
determi
nes
eitherthe the
next
DAC
output
or an end
of
conversion.
Converted
data
is then
processed
by
the
Lexichip with
instructions
from its WCS.
DAC logic
signals
are
provided
by
the
Lexichip to
control
the Sample and Hold
(SAH)
and deglitch functions
and conversion data
latching.
A
Word
Clock
signal (WC/)
is
used as a
clock
reference and
indicates
the
beginning
of
a
conversion
cycle.
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