9. Word Clock
9.1 Operation and Technical Background
Correct interpretation of digital audio data is dependent upon a definite sample frequency. Digi-
tal signals can only be processed or transferred between devices if these share the same clock.
Otherwise the signals are misinterpreted, causing distortion, clicks/crackle or dropouts.
AES/EBU, SPDIF and ADAT are self-clocking, so an additional line for word clock could be
considered redundant. In practice however, using several devices at the same time can cause
problems. For example, if devices are connected in a loop without there being a defined ‘mas-
ter’ device, self-clocking may break down. Besides, the clocks of all devices must be synchro-
nized from a single source. Devices without SPDIF inputs (typically playback devices such as
CD players) cannot be synchronized via self-clocking.
In digital studios, synchronization requirements can be met by connecting all devices to a cen-
tral sync source. For instance, the master device could be a mixing desk, sending a reference
signal - word clock - to all other devices. However, this will only work if all the other devices
have word clock inputs (e.g. some professional CD players) allowing them to run as slaves.
This being the case, all devices will receive the same clock signal, so there is no fundamental
reason for sync problems when they are connected together.
But word clock also has some disadvantages. The word clock is based on a fraction of the ac-
tually needed clock. For example SPDIF: 44.1 kHz word clock (a simple square wave signal)
has to be multiplied by 256 inside the device using a special PLL (to about 11.2 MHz). This
signal then replaces the one from the quartz crystal. Big disadvantage: because of the high
multiplication factor the reconstructed clock will have great deviations called jitter. The jitter of
a word clock is typically 15 times higher as when using a quartz based clock.
The end of these problems should have been the so called Superclock, which uses 256 times
the word clock frequency. This equals the internal quartz frequency, so no PLL for multiplying is
needed and the clock can be used directly. But reality was different, the Superclock proved to
be much more critical than word clock. A square wave signal of 11 MHz distributed to several
devices - this simply means to fight with high frequency technology. Reflections, cable quality,
capacitive loads - at 44.1 kHz these factors may be ignored, at 11 MHz they are the end of the
clock network. Additionally it was found that a PLL not only generates jitter, but also also rejects
disturbances. The slow PLL works like a filter for induced and modulated frequencies above
several kHz. As the Superclock is used without any filtering such a kind of jitter and noise sup-
pression is missing. No wonder Superclock did not become a commonly accepted standard.
The actual end of these problems is offered by RME's SteadyClock technology. Combining the
advantages of modern and fastest digital technology with analog filter techniques, re-gaining a
low jitter clock signal of 11 MHz from a slow word clock of 44.1 kHz is no problem anymore.
Additionally, jitter on the input signal is highly rejected, so that even in real world usage the re-
gained clock signal is of highest quality.
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