Trio64V+ Integrated Graphics/Video Accelerator
S3
Incorporated
10.2 INPUT PROCESSING
........
10-4
10.2.1 Primary Stream Processing
..
10-4
10.2.2 Secondary Stream Processing. 10-5
10.3 COMPOSITION/OUTPUT
......
10-5
10.3.1 Opaque
Rectangular Overlaying 10-6
10.3.2
Blending
........
. 10-7
10.3.3 Color/Chroma
Keying.
. 10-8
10.3.4
Window
Location.
. . . . 10-8
10.4 STREAMS FIFO CONTROL.
. 10-8
Section
11:
Local Peripheral
Bus
11-1
11.1
Scenic/MX2 INTERFACE
......
11-2
11.1.1 Scenic/MX2 Register/Memory
Access
..............
11-2
11.1.2 Scenic/MX2
Compressed Data
Transfer . . . . . . . . .
..
. 11-4
11.1.3 Scenic/MX2 Video
Capture
..
11-5
11.2
DIGITIZER INTERFACE
..
.11-7
11.2.1 1
2
C Register
Interface.
.11-7
11.2.2
SAA7110Videolnput.
.11-8
11.3
CL-480INTERFACE...
.11-9
11.4 HOST PASS-THROUGH 11-10
11.5 LPB-ENABLED PIN
ASSIGNMENTS.
. . . . 11-10
Section
12:
Miscellaneous
Functions
.............
12-1
12.1
VIDEO BIOS ROM INTERFACE
...
12-1
12.1.1 Disabling BIOS ROM Accesses
12-1
12.1.2 BIOS ROM Hardware Interface
12-1
12.1.3 BIOS ROM Read Functional
Timing
..............
12-2
12.1.4
BIOS ROM Address
Mapping
. 12-2
12.2 GREEN
PC
SUPPORT. . . . 12-4
12.3 GENERAL
INPUT
PORT
. . 12-4
12.4 GENERAL
OUTPUT PORT . 12-5
12.5 FEATURE
CONNECTOR
INTERFACE
. . . . . . . . . 12-7
12.6
SERIAL COMMUNICATIONS
PORT
. . . . . . . . . . . . .
12-11
12.7 INTERRUPT GENERATION. .
12-11
Section
13:
Basic Software
Functions . . . . . . . . . .
13-1
13.1
CHIP WAKEUP
...........
13-1
13.2 REGISTER ACCESS
.........
13-2
13.2.1
Unlocking
the
S3
Registers . 13-2
13.2.2 Locking
the
S3
Registers.
. 13-3
13.2.3 Unlocking/Locking
Other
Registers
............
13-3
iv
13.3 TESTING
FOR
THE
PRESENCE
OF
A Trio64V+
CHIP
...
13-4
13.4
GRAPHICS MODE SETUP
...
13-4
Section
14:
VGA Compatibility
Support
............
14-1
14.1
VGACOMPATIBILITY.
. . . .
14-1
14.2 VESA
SUPER
VGA SUPPORT 14-2
Section
15:
Enhanced
Mode
Programming
..........
15-1
15.1 LINEAR ADDRESSING
FOR
DIRECT
VIDEO MEMORY
CPU
ACCESSES
15-1
15.2 VIDEO MEMORY ACCESS THROUGH
THE
GRAPHICS ENGINE . . .
..
15-2
15.3
MEMORY MAPPING
OF
REGISTERS
...........
.
15.3.1
Backward-Compatible
MMIO
15.3.2
New
MMIO
.......
.
15.4
PROGRAMMING
.....
.
15.4.1 Notational
Conventions
15.4.2 Initial Setup
......
.
15.4.3
Programming
Examples
15.4.3.1
Solid Line
.....
.
15.4.3.2 Textured Line
...
.
15.4.3.3 Rectangle
Fill Solid .
15.4.3.4
Image
Transfer-Through
15-4
15-4
15-6
15-7
15-7
15-8
15-8
15-9
15-10
15-12
the
Plane
..........
15-13
15.4.3.5 mage
Transfer-Across
the Plane
..........
15-15
15.4.3.6
BitBLT-Through
the Plane 15-17
15.4.3.7 BitBL T
-Across
the Plane . 15-18
15.4.3.8
PatBLT-Pattern
Fiii
Through
the Plane
.....
15-20
15.4.3.9
PatBLT-Pattern
Fill Across
the
Plane . . . . . . .
..
15-21
15.4.3.10
Short Stroke Vectors
..
15-22
15.4.3.11 Programmable Hardware
Cursor . . . . . . . . 15-23
15.5
RECOMMENDED READING
..
15-24
Section
16:
VGA Standard Register
Descriptions
...........
16-1
16.1
16.2
16.3
16.4
16.5
GENERAL REGISTERS
....
.
SEQUENCER REGISTERS
..
.
CRT
CONTROLLER REGISTERS
GRAPHICS CONTROLLER
REGISTERS
..........
.
ATTRIBUTE CONTROLLER
REGISTERS
...........
.
",
.
IU-I
16-5
16-21
16-36
16-43
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