Trio64V+ Integrated Graphics/Video Accelerator
S3
Incorporated
#
2-1
3-1
3-2
4-1
4-2
4-3
4-4
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
8-1
9-1
10-1
10-2
11-1
11-2
vi
List
of
Figures
Title Page
208-pin
PQFP
Mechanical
Dimensions . . . . . . . .
2-2
Trio64V+
PCI
Bus
Pinout-
LPB
Mode
. . . . . . . . .
3-2
Trio64V+ VL-Bus Pinout -
LPB
Mode
. . . . . . . . 3-3
Clock Waveform
Timing
4-4
Input
Timing
..
. . 4-5
Output
Timing
. . . . 4-7
ResetTiming
. . . . .
.4-10
Basic
PCI
Read
Cycle . 6-2
Basic
PCI
Write
Cycle.
6-2
PCI
Disconnect Example A . 6-3
PCI
Disconnect Example B . 6-3
PCI
Configuration Write Cycle 6-4
PCI
Configuration
Read
Cycle 6-4
Read
Parity Operation . . . . 6-5
VL-Bus Read Cycle . . . . . .
6-7
1 Wait-state VL-Bus Write
Cycle.
6-8
1-
or
2-MByte DRAM
Configuration . . . . . . . .
..
7-2
4-MByte DRAM
Configuration.
7-3
Fast Page Mode Read
Cycle
..
7-4
Fast Page Mode
Write
Cycle
..
7-5
Fast Page Mode Read/Modify/
Write
Cycle . . . . . . . . .
..
7-6
EDO
Mode
Read
Cycle . . .
..
7-7
EDO
Mode Read/Modify/Write
Cycle
.............
" 7-8
1-Cycle
EDO
Mode
Read/Write 7-9
1-cycle
EDO
Read/Modify/Write
Cycle
................
7-10
Internal
RAMDAC Block Diagram
8-1
PLL
Block Diagram . . . . . . 9-2
Streams Processor . . . .
..
.
10-1
Screen Definition Parameters . 10-5
LPB
Internal Block Diagram .
11-1
Trio64V+
to
Scenic/MX2
Hardware
Interface
....
, . 11-2
#
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-10
11-11
11-12
11-13
11-14
11-15
12-1
12-2
12-3
12-4
12-5
12-6
12-7
12-8
Title Page
Scenic/MX2 Write
(Scenic/MX2 Ready) 11-3
Scenic/MX2 Write
(Scenic/MX2
Not
Ready) 11-3
Scenic/MX2
Read
(Scenic/MX2 Ready)
..
11-3
Scenic/MX2
Read
(Scenic/MX2
Not
Ready) 11-3
Scenic/MX2 Compressed
Transfer (Ready)
....
11-4
Scenic/MX2 Stopping a
Compressed Xfer . . . . 11-5
Scenic/MX2
VSYNC and
HSYNC Protocols . . . . 11-5
Scenic/MX2
Video
Input
(Trio64V+ Ready) . . . . 11-6
Scenic/MX2
Video
Input
(Trio64V+
Not
Ready) . . 11-6
Tri064V+
to
SAA7110 Digitizer
Interface
. . . . . . . . 11-7
16-
to
8-bit Video Data
Conversion
......
11-8
Video
81n or
16
Mode
Input
11-8
Video 8
In or
16
Mode
Input
11-9
BIOS ROM
PCI
Configuration
Interface.
. . . . . . . . .
..
12-1
BIOS ROM VL-Bus Configuration
Interface . . . . . . . . . . . 12-2
BIOS ROM
Read
Functional
Timing
-
PCI
. . . . . . . . . 12-3
General
Input
Port Interface
(VL-Bus) . . . . . . . . . . . 12-4
General
Input
Port
Timing
(VL-Bus) . . . . . . . . . . . 12-5
General I/O Port
Timing
(PCI)
12-5
General
Output
Port Interface
(VL-Bus) . . . . . . . . . . . 12-6
General Output Port
Timing
(VL-Bus) . . . . . . . . . . . 12-6
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