S3 Incorporated Trio64V+ - Table of Contents

II·
Tri064V+ Integrated Graphics/Video Accelerator
S3 Incorporated
Table of Contents
List of Figures
vi
List of Tables. . viii
Section 1: Introduction . 1-1
1.1 OVERViEW............. 1-2
1.2 S3 STREAMS PROCESSOR . . .. 1-2
1.3 S3 SCENIC HIGHWAY . . . . . .. 1-3
1.4 Trio64V+ CHANGES FROM THE
Trio64 . . . . . . . . . . . . . . .. 1-3
Section 2: Mechanical Data . . .. 2-1
2.1 THERMAL SPECIFICATIONS. 2-1
2.2 MECHANICAL DIMENSIONS .,. 2-1
Section 3: Pins . . . . . . . . . .. 3-1
3.1 PINOUT DIAGRAMS ........ 3-1
3.2 PIN DESCRIPTIONS ........ 3-4
3.3
PIN LISTS .............. 3-12
Section 4: Electrical Data ..... 4-1
4.1 MAXIMUM RATINGS ....... 4-1
4.2 DC SPECIFICATIONS. . . . . . . . 4-1
4.3 AC SPECIFICATIONS . . . . . . . . 4-3
4.3.1 RAMDAC AC Specifications . . 4-3
4.3.2 Clock Timing . . . . . . . . .. 4-4
4.3.3
Input/Output Timing . . . . . . 4-5
Section 5: Reset and Initialization 5-1
Section 6: System Bus Interfaces. 6-1
6.1 PCI BUS INTERFACE . . . 6-1
6.1.1 PCICONFIGURATION ..... 6-1
6.1.2 PCI Bus Cycles . . . . . . . .. 6-1
6.2 VL-BUS INTERFACE . . . . . . . . 6-6
6.2.1 VL-Bus Cycles. . . . . . . . . . 6-6
6.2.2
SRDY Generation. . . . . . .. 6-6
Section 7: Display Memory .... 7-1
7.1 DISPLAY MEMORY
CONFIGURATIONS
......... 7-1
7.2 DISPLAY MEMORY REFRESH ... 7-4
7.3
DISPLAY MEMORY FUNCTIONAL
TIMING
...... . . . . . . .. 7-4
7.4
1-CYCLE EDO DRAM SUPPORT. 7-9
7.5
DISPLAY MEMORY ACCESS
CONTROL. . . . . . . . . . . .. 7-11
Section 8: RAMDAC Functionality 8-1
8.1 OPERATING MODES ........ 8-1
8.2 COLOR MODES . . . . . . . . . . . 8-2
8.2.1 8 Bits/Pixel - Mode 0 . . . . . . 8-2
8.2.2
Output-doubled 8 Bits/Pixel -
Mode 8
............. 8-2
8.2.3 15/16-Bits/Pixel - Modes 9
and
10 .............. 8-3
8.2.4 Packed 24 Bits/Pixel - Mode 12. 8-3
8.2.5 24
Bits/Pixel - Mode 13 . . . . . 8-3
8.3 RAMDAC REGISTER ACCESS . . . 8-3
8.4 RAMDAC SNOOPING. . . . . . . . 8-3
8.5
SENSE GENERATION ....... 8-3
8.6
POWER CONTROL . . . . . . .. 8-3
Section 9: Clock Synthesis and
Control ............... 9-1
9.1 CLOCK SYNTHESIS ......... 9-1
9.2 CLOCK REPROGRAMMING .... 9-2
9.3
DCLK CONTROL .......... 9-3
Section 10: Streams Processor . 10-1
10.1 INPUT STREAMS. . . . . . . .. 10-1
10.1.1 Primary Stream Input .... , 10-2
10.1.2 Secondary Stream Input
.. , 10-2
10.1.3
Hardware Cursor Generation 10-2
10.1.4
Frame Buffer Organization/
Double Buffering ...... , 10-2
iii