Sansui Micro-750-D - Page 13

D1870 BLOCK DIAGRAM
RFZC/
TEZC
Circuit
RF flag
Interface
Data
Slicer
Data
PLL
Servo
ADC
Serial RF
Controller
Servo
DSP
PDM &
PWM
DAC
Flags &
Program-
mable
I/O
Varipitch
CLV Clock
Generator
PWM
DAC
CLV/CAV
Controller
EFM/EFM+
Demodulator
Subcode/ID
Demodulator
Sync
Protection
CIRC/RSPC
Error Corrector
CDROM
Sync Detection
Descrambler
C3
Decoder
Varipitch System
Clock
Generator
DRAM
Clock
Generator
Reset
Logic
Buffer
Memory
Controller
256
SRAM
Key/LED
Interface
Mega
Interface
Micro-controller
Interface
CSS
Host
Data
FIFO
ATAPI
Packet
FIFO
Host/MPEG Interface
System Clock
RFRPSLV
TEZI
TEZISLV
HRFZC
ADCVDD
FEI
TEI
RFRP
RFLEVEL
ADIN
ADCVSS
SLCK
SDEN
SDATA
FDO
TRO
FMO
PWMOUT1
PWMOUT2
PDMVDD
PWM2VREF
PWMVREF
PDWVSS
FLAGA
FLAGB
FLAGC
FLAGD
IO[3:0]
TEST
PRST#
RD[15:0]
RA[11:0]
RAS#
CAS#
CASH#/RWEH#
RWE#
ROE#
CLK
CKE
DOM
BA(1:0)
EJ/STOP#
PLY#/PAU#
LED
TRAYIN#
TRAYOUT#
LIMIT#
TROPENPWM
TRCLOSE
BDO RFDTSL SCO RF N RF P PLLVDD
REF
LPFN LP N PLLVSS J TFN PDO LPFO LP P VBDPLL J TFO XTALO XTAL
PLLVDD PLLVSS
DMVDD DMVSS URST#
VPVDD
VCOC N
VPVSS
ENDM
FG
DMO
HD[15 0]
PD AG#
DASP#
HRST# D OW#
D OR#
DMACK#
HA[2 0]
CS1FX# CX3FX#
DMARQ
ORDY
NTRQ
OCS16#
URD#
UALE
UCS1 UCS2
UWR#
U NT#
UAD[7 0]
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