Sanyo MCD-Z530F - IC102 LC78622 NE (Digital Signal Processor)

IC BLOCK DIAGRAM & DESCRIPTION
ICI 02 LC78622NE (Digital Signal Processor)
No. Pin Name
Vo
Function
1 DEFI
I Input terminal for detect signal of defect
2 TAI
I Input terminal for test.
3 PDO o The phase comparison output termmal for
external VCO control.
4 VVss
-
Ground terminal for built-in VCO
5 ISET
I Resistance connection terminal for
electric current adjustment of PDO output.
6
VVDD
- Built-in VCO power supply terminal.
7 FR
I VCO frequency range adjustment.
8
Vss - Ground for Digital
9
EFMO o EFM signal output terminal for slice level control.
10 EFMIN
I EFM signal input terminal for slice level control.
11
TEST2 I TEST pin. Normal time is non connection.
12
CLV+
o Output terminal for Disc motor control.
13
CLV-
0 Output terminal for Disc motor control.
14
VIP
o Change of rough servo I phase control
Rough servo: “H”, Phase control : “L
15 HFL
I Input terminal of track search signal.
16 TES
I Input terminal of tracking error signal.
17
TOFF o Output terminal of tracking off.
18
TGL
o Output terminal for change of tracking gain.
19 JP+ o Output terminal for tracking jump control.
al JP-
0 Output terminal for tracking jump control.
21 PCK
o Clock monitor output terminal for EFM data
playback. (4,321 8 MHz)
’22
FSEQ o Output terminal for detect of SYNC signal.
23 DVDD
- +5V
24 CONT1
1/0
25 CONT2 1/0 This output can control at serial control from
26
CONT3 1/0 micro processor.
27 CONT4
1/0
28
CONT5
1/0
29
EMPH
o Output terminal of de-emphasis monitor.
“H” : de-emphasis
3) C2F o Output terminal of C2 flag
31
DOUT o Output terminal of digital out
No.
Pin Name
I/o
Function
32 TEST3
I
Test pin.
X3 TEST4
I
Test pin,
34 NC
-
Non connection.
% MUTEL
o
Mute output terminal for L-ch
36 LVDD -
Power supply for L-ch
37 LCHO
o
Output terminal for L-ch
38 LVSS
-
GND for L-ch
39
RVSS
-
GND for R-ch
40 RCHO
o
Output terminal for R-ch
41 RVDD -
Power supply for R-ch
42 MUTER
o
Mute output terminal for R-ch
43 XVDD - Power supply of crystal oscillation
44
XOUT
o Connection terminal of crystal oscillation (16.9344MHz)
45 XIN
I Connection terminal of crystal oscillation (16.9344MHz)
46 Xvss GND of crystal
oscillation
47
SBSY
o
Output terminal for synchronizing signal of
I
sub-cord block
‘WI EFLG
I O 10utput terminal for correction monitor of Cl, C2,
Single and Double
49
Pw o
Output terminal for sub-cord of P, Q, R, S, T, U and W
50 SFSY
o
Output terminal for synchronizing signal of
sub-cord frame
51
SBCK
I
Input terminal for readout clock of sub-cord
S? FSX
o
Output terminal of Synchronizing signal (7.35kHz)
53 WRQ
o
Output terminal for standby of sub-cord Q output
54 RWC
I
Input terminal of read I write control
55
SQOUT
o
Output terminal of sub-cord Q
% COIN
I
Input terminal of command from micro processor
57 CQCK
I
Clock input for reading sub-cord from SQOUT
58
RES
I
Reset (turn on: L)
59 TST11 o
Test pin
m
16M o
16.9344 MHz
61 4.2M
o
4.2336 MHz
62 TEST5
I
Test pin
63 Cs
I
Chip select terminal
64
TEST1
I
Test pin
TST1l TEST2 TES14
EFMO VVDD VVS’5
PW (SET Ffl PCK Thl TES1l 1EST3 TEST5 VIXI v=
VCO Clcck Osc!llator
I
FSEQ@
s“ ‘
Dqlai Attenuator
&
WRQ
ttt
t+
1,,
7-R
lbd DAC
=K
L,P,F
Xlal Root
Tnmng Generator
CC+4T2 cOti?4 XOUT RVSS MUTER LVSS
“criiiLLQ
C2F
DOUl
(NC)
-11-