5-14
holding OFF the HIGHBAND VCO through diode CR10. Steering diodes CR17
and CR18 are used to provide isolation between the two OFF VCOs and the active
output.
The output from the selected VCO is passed through prescaler, U23 where the
signal is divided by two. The prescaler output is buffered by MMIC, U24, before
being sent to the first mixer. The VCO output is also passed through dual buffer
amplifiers U39A and U39B. The output signal from U39B provides the VCO signal
to the synthesizer chip U21. Using separate amplifiers in this fashion improves the
isolation between the receiver mixer circuitry and the input to the synthesizer chip.
Serially loaded PLL chip U21 provides a reference counter, divide-by-N counter, a
phase/frequency detector and the VCO control register. The PLL reference
frequency is derived from the 12.288 MHz Master Clock. Loop filtering and level
shifting of the PLL phase detector output is accomplished by active filters U22A/B.
5.4.4
THE SECOND LOCAL OSCILLATOR SYNTHESIZER
The second local oscillator synthesizer consists of PLL chip U17, 45.040 MHz
Colpitts oscillator FET Q12, and buffer amplifier Q13, U18A, U18B and Q33.
Buffer amplifier U18A provides a sample of the 45.040 MHz VCO signal for the
synthesizer chip while U18B provides 45.040 MHz drive for the second mixer.
5.5
THE 2187.5 kHz MONITOR RECEIVER
5.5.1
BLOCK DIAGRAM
Figure 5.5.1 shows the block diagram of the 2187.5 kHz monitor receiver, required
for GMDSS applications is Sea Area 2. The receiver is a single channel, dual
conversion design which uses a single crystal to provide both conversion signals.
The first IF frequency is 455 kHz, the second IF frequency is nominally 14.583 kHz.
As in the SEA 245 Main Receiver, the DSP engine provides all channel selectivity,
signal demodulation, and AGC.
5.5.2
RECEIVER RF CIRCUITRY AND FIRST MIXER
Antenna input to the 2187.5 monitor receiver is on pins 13 (signal) and 14 (ground)
of the rear panel Accessory Connector. The impedance is 50 ohms and provisions
have been made to support the SEA 7002 Active Antenna, should this be desired.
The RF signal first passes through a high pass filter and then a low pass filter to Q9,
the preamplifier. The preamplifier is a grounded-gate JFET with tuned drain circuit.
The nominal gain of this stage is about 8 dB with the drain voltage on. As in the
Main Receiver, a gain step is provided by switching the drain voltage off under
control of the AGC program in the DSP. The combination of the front end 5-
section low pass filter and the low pass response of the preamplifier drain circuitry
combine to provide the receiver with better than 75 dB rejection of the 3097.5 kHz
primary image.
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