SEA 245 - +24 VTX Rail and PA Bias System; Mainboard Controller and DSP Processors; Controller and DSP Processors Overview; Processor Assembly Block Diagram

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circuitry.
5.6.9 THE +24VTX RAIL AND PA BIAS SYSTEM
Bias for the PA output transistors is generated from the +24VTX rail. Since the
entire +24 volt power source is isolated from the chassis, an optical isolator, U5 on
the PA/Filter Assembly (ASY-0245-02) is used to switch on a P-channel FET (Q12)
when the +12VTX rail is energized. This +24VTX line is then used to power bias
regulator transistor Q8 and the +9V PA bias supply regulator U4. The output from
U4 powers bias tracking amplifier transistor Q9. Q9 is a small power device which
is bonded to the same heat sink as the RF power transistors to provide thermal
feedback.
5.7 THE MAINBOARD CONTROLLER AND DSP PROCESSORS
5.7.1 GENERAL
The Mainboard microcontroller and digital signal processor (DSP) are contained on
a separate assembly (ASY-0245-04). The microcontroller is a Motorola
MC68C812A4 operating from a 6.144 MHz clock. This is a low voltage (3.3V) 16-
bit processor with two asynchronous serial ports, a serial peripheral interface (SPI),
a timer and pulse accumulator module, an 8-channel 8-bit A/D converter, 1 Kbyte of
RAM, 4 Kbytes of EEPROM and memory expansion logic with chip selects. It also
has many bidirectional ports for general purpose I/O. The DSP is a TI
TMS32OVC5402. This is a 32-bit fixed-point DSP capable of 100 MIPS operation.
It includes 16 Kwords (16-bit) of internal RAM, two sophisticated multichannel
serial ports and a parallel host port interface.
5.7.2 BLOCK DIAGRAM
Figure 5.7.1 shows a block diagram of the processor assembly.
5.7.3 CLOCK DISTRIBUTION
The 12.288 MHz master clock is supplied through P2 to the processor assembly
(ASY-0245-04). U11A divides this clock by two to provide a 6.144 MHz clock to
the microcontroller, U5. U9 buffers the clock and converts it to a 1.8 volt level
suitable for the DSP, U7. The DSP has an internal PLL which generates a 98.304
MHz clock phase locked to the 12.288 MHz reference. The 98.304 MHz clock is
used as the cycle clock for the DSP and is also divided by 4 by U10 to produce a
24.576 MHz clock for the CODEC, U1. This clock divider can be reset by the DSP
in order to insure a known phase relationship between the CODEC clock and the
DSP clock. This is necessary for reliable communication between the CODEC and
the DSP.