Sharp 19SV111 - Page 21

19SV111
BlOCK DIAGRAM (continued)
H
IC 1 and IC4: R H - i X 1 2 4 5 C E Z Z
PIN_S ARRANGEMENT
Az tO
24
Vee
A()
2
23
A a
Pin Function
As
3 22
Ag
G
Ao-A,
Address Input
cs Chip Select
A4
4 21
WE
A3
5
20
OE
A2
6
19
bo
OE Output Enable A, 7
18 cs
WE Write Enable
Ao
8 17
1/0s
1/0
1
-l/Oa Data l nput I 0 utput
11 o,
9
16
l/Oz
l/02
10 15
l/06
Vee
Power
1/03
11
14
l/Os
F
GND Ground
GND
12
13
l/04
BLOCK DIAGRAM
E
Ao
As
cv-
~ ~
®---
-+-------@ Vee
A6
®----
ROW ROW MEMORY CELL
~
GND
Az
As
Ag
D
A,(j
0-
ADDRESS DECODER
ARRAY
®--
BUFFER
(128 X 128)
CfP-
®---
- -
lcs
.........
L...-""
110,
1/02
c
1/03
9
~
SENSE AMP_
......
~
COLUMN
10
~
""""'~
~
DECODER
11
---.....
1/04
1/0
5
[ /06
13
DATA
~
CONTROL
-
~
14
COLUMN
15
ADDRESS
l/Oz
B
r /Oa
16
BUFFER
17
lcs
A
18
}>---
J
21
4
7
6
5
20
~
A4 A,
A2 A3
2
3 4
5 6
23