LC-37D90U
5 – 34
L4 AVSS_OUTBUF --- 3.3V ground for output.
AD27, AG27 LVDS_VSSO --- LVDS out buffer ground.
AE24 LVDS_VSSD --- LVDS Digital ground.
AF27 LVDS_VSSA --- LVDS analog ground.
AH27 LVDS_VSSP --- LVDS PLL ground.
AH28 LVDS_VDDP --- LVDS PLL power.
AF28 LVDS_VDDA --- LVDS analog power.
AE28 LVDS_VDDD --- LVDS Digital power.
AD28, AG28 LVDS_VDDO --- LVDS out buffer power.
Ball Assignments for Reference Voltage.
M1 VREFP_1 --- ADC1 voltage reference +.
M2 VREFN_1 --- ADC1 voltage reference -.
V3 VREFP_2 --- ADC2 voltage reference +.
V4 VREFN_2 --- ADC2 voltage reference -.
Y3 VREFP_3 --- ADC3 voltage reference +.
Y4 VREFN_3 --- ADC3 voltage reference -.
R3 VREFP_4 --- ADC4 voltage reference +.
R2 VREFN_4 --- ADC4 voltage reference -.
Miscellaneous Ball Assignments.
A6 RESET I System reset powered by VDDH/VSS. RESET# forces the chip to a known state. This
pin should be tied to CPU reset.
A7 INTN I/O Interrupt signal (active low) powered by VDDH/VSS.
C7 PWM0 I/O General purpose I/O.
D7 PWM1 I/O General purpose I/O.
C8 TESTMODE0 I Reserved (Connected to ground).
D8 TESTMODE1 I Reserved (Connected to ground).
A1, B2 GPIO 0, GPIO 1 I/O Programmable general purpose I/O.
F2, F3, E3, E2, E1, D1,
D2, D3, C3, C2, C1, B1
AUDIO_P [11:0] I/O Audio Data Input/Output.
B13 MCU_CS I Initial LX setting for choosing I2C address & CPU bus Configuration.
C13 MCU_CSN I Initial LX setting for choosing I2C address & CPU bus Configuration.
LVDS Output Ball Assignments.
AK27 TCLK2M O LVDS 2nd Channel Differential negative CLK out.
AJ27 TCLK2P O LVDS 2nd Channel Differential positive CLK out.
AK25 TE2M O LVDS 2nd Channel Differential negative data out.
AJ25 TE2P O LVDS 2nd Channel Differential positive data out.
AK26 TD2M O LVDS 2nd Channel Differential negative data out.
AJ26 TD2P O LVDS 2nd Channel Differential positive data out.
AK28 TC2M O LVDS 2nd Channel Differential negative data out.
AJ28 TC2P O LVDS 2nd Channel Differential positive data out.
AB29 TA1P O LVDS 1st Channel Differential positive data out.
AB30 TA1M O LVDS 1st Channel Differential negative data out.
AC29 TB1P O LVDS 1st Channel Differential positive data out.
AC30 TB1M O LVDS 1st Channel Differential negative data out.
AD29 TC1P O LVDS 1st Channel Differential positive data out.
AD30 TC1M O LVDS 1st Channel Differential negative data out.
AF29 TD1P O LVDS 1st Channel Differential positive data out.
AF30 TD1M O LVDS 1st Channel Differential negative data out.
AG29 TE1P O LVDS 1st Channel Differential positive data out.
AG30 TE1M O LVDS 1st Channel Differential negative data out.
AE30 TCLK1M O LVDS 1st Channel Differential positive CLK out.
AE29 TCLK1P O LVDS 1st Channel Differential negative CLK out.
AK30 TA2M O LVDS 2nd Channel Differential negative data out.
AJ30 TA2P O LVDS 2nd Channel Differential positive data out.
AK29 TB2M O LVDS 2nd Channel Differential negative data out.
AJ29 TB2P O LVDS 2nd Channel Differential positive data out.
AH29 TF1P O LVDS 1st Channel Differential positive CLK out.
AH30 TF1M O LVDS 1st Channel Differential negative CLK out.
AJ24 TF2P O LVDS 2nd Channel Differential negative data out.
AK24 TF2M O LVDS 2nd Channel Differential positive data out.
Pin No. Pin Name I/O Pin Function
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