6
Pin Signal
IN/OUT
Desc
r
iption (Standby
=
power
off)
No
.
name
51
Voe
OUT
LCD power
s
upply
,
high during
s
t
andby and low when the high
lev
e
l
clock
stops
.
52
VGG
IN
Power supply normally low.
53
08
IN/OUT
Data
bus
,
normally high
impedance
.
54
07
IN/OUT
Data bus, normally high impedance.
55
06
IN/OUT
Data bus, normally high
impedance
.
56
05
IN/OUT
Data bus, normally high
impedance
.
57
04
IN/OUT
Data bus, normally high impedance.
58
03
IN/OUT
Data
bus
,
normally high
impedance
.
59
02
IN
/
OUT
Data bus, normally
h
i
gh
impedance.
60 01
IN/OUT
Data bus, normally high
impedance
.
61
Fo5 OUT
External system ROM chip enable (CE1).
62
Fo4 OUT
Expansion RAM
(PC
·
1251 RAM) chip enable
(CE2)
.
63
Fo3 OUT
Basic RAM
(PC
-
1250
,
PC
-
125
1)
chip enable (CE3).
64
Fo2 OUT Data out
(Do
u
t)
,
data
outpu
t
port
to
pe
r
ipheral.
65 Fo1 OUT
BUSH
l
/
F
output
port output.
66
Bo8 OUT
LCD driver LSI chip enable (CE4).
67
Bo7 OUT
A
14
.
Address bus,
h
i
gh
during
s
t
andby
.
68 Bo6 OUT
A13
.
Ad
dr
ess
bus
,
h
i
gh
duri
ng
standby
.
69 Bo5 OUT
A
12
.
Address bus,
h
i
gh
during
s
t
a
ndby
.
70 Bo4 OUT
A
11
.
Address
bus
,
high during standby.
71
Bo3 OUT
A
10
.
Address bus, high
dur
i
ng
standby
.
72
Bo2 OUT
A9.
Address
bus
,
h
i
gh
during
standby
.
73
Bo1 OUT AS.
Address
bus
,
high
duri
n g
standby.
74 Ao8 OUT
A7
.
Address
bus
,
high during
standby
.
75 Ao7 OUT
A6
.
Address bus, high
dur
i
ng
standby.
76 Ao6 OUT
A5
.
Address
bus
,
high
dur
i
ng
standby.
77 Ao5 OUT
A4
.
Address bus, high
dur
i
ng
standby
.
78 Ao4 OUT
A3
.
Address
bus
,
high during standby.
79 Ao3 OUT
A2
.
Address
bus
,
high
du
r
ing standby.
80
Ao2 OUT
A
1.
Address bus, high during standby.
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