Sharp PC-1500 - Page 110

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4-3-4. 1/0 PC
When the pin 'fo. 34 (M FO) of thr I 0 PC is connected \\ith ME I of the CP U. it will be
accessed as the ME I area.
0 PC-1500 1/0 PC
Pin no .
Signal name Descrip tio n
1
PA I Key str obe
2 PA2 K~s tr obe
3
f.>A3
~s tr obe
4 PM
-I
K~ s tr obe
:,
PAS K~s tr obe
6
PA6
K~s tr obe
7 P/17
K~strobc
8 GND
GND
9 PBO
Not used
10 PB1 Not used
•
Scr~al data 1ne;ut l rom the cassette raoo 11 PB2
I
12 PB3 VCC (e xport model). GND (domes1 1c model)
13 PB4 GND
14 PBS T 1 mcr cont rot
IS
PS6
Ti
mer co n tro l
16
PB7
ONk ~ 1 npu1
17 P<i> GN D
18 P CO Timer con t ro l
19 PCI Timar con t ro l
20
PC2 l 1mcr control
21
PC3
Timer con t rol
22 PC4
Tinier con t rol
23 PCS
Timer
con t rol
24 PC6 Buzzer on / olf control
25 PC7 Not used
26
cso C t11 1>_se1ec1 (AD12l
27 CS1 Ch ip selec1 ( A013 )
28
~
Ch.!2._ select
29
RSO Chi p select ( ADO)
30
RS I Chip setect ( AD lJ
31
RS2
Chip sel ect (AD2)
32 RS 3
Chip sel ect (AD3)
33 R/W M emory rc ad / v1 ri te
34 MEO M EO area das1gnat 1on
35
ME I ME 1 ar ea dcs..!2._n at ion
36
WO WAIT co nditio n inp ut
37 W t WAIT condition input
38 GND GNO
39 vcc vcc
40 DMEO Chip select taki ng consideration ol WAIT condition (assignment ol
MEO arc&
41 OMEl Chip select taki ng conside rahon ol WAil condition (assignment of
MEI a1ea )
42
WAIT WA IT to CPU
-
43 INT Interru pt to CPU
••
RESET --!
ltO PQrt reset in put
45 IRO Interrupt input
46 (l)OS Basic cl oc k i npu t
47
cu CMT demodulation cl oc k •<£ul
•8 SDl
VCC level
49
LC Not used
50 CLO C MT signal
51 soo Serial data ou~ t to casselte 1~ _ e
52 DO Dal a. bus
53
Dl Data bus
54
02
Data bus
55 03
Data bus
56
04
Data bus
57
05 Data bus
58 06 Data bus
-
59 07 Oa1a bus
60
P AO Key s1robe
105
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