All and more about Sharp PC-1500 at http:/lwww.PC-1500.info
Q)
MSK register
MSK
7 6 5 4 3 2 0
lx l
xlx
lx l
Interrupt mask
bi
t for IRQ
-,
I
I
I
'----7
-
Interrupt mask bit for PB?
)
) Interr
up
t mask bit for receiver flag RD
l
Inter
rup
t mask
bit
f
or
tr
ansm
it
1er
fl
ag
TD
Inter
rup
t enabled when the b
it
is '
'1"
.
The
MS
K r
eg
ister can readfwrite
data
when register is selected (10 10).
NOT
E: Wh
en
the contents
of
the MSK register are read, the
conte
n
ts
of
CL1. SD1. PB7.
and
IRO are stored in
high
order digit
pos
i
tion
s.
** !
cu
is
o1
l
re
1i
1
Ro
l
M
~ K
I
M
~ K
I
M
fK
I
M8K
I
Contents
of
MSK read
© IF register
IF
7 6 5 4 3 2 1 0
I x I x I x I x I
TD
I
RD
I
1
~
I
1
~
I
I
I
~
Set at the rising e
dge
of
I
RQ
in
put.
l Set at the risi
ng
edge
of
PB7 input.
l Set u
po
n
comp
leti
on
of
serial input receive.
RO
is
reset when the CPU received data is
read
or
th
e contents
of
the U register are read.
Set
upon
complet
i
on
ol
serial data
tr
ansmission.
Reset when t
he
CPU load
th
e tran
sferr
ing
serial data to the L
re
gist
er.
IFO
and
IFI
can readfwrite
da
ta when register is selected (
IOI
I).
RD
and
TD
ar
e dedicated to read
on
ly.
NOTE: Duri
ng
receive
of
serial data, RD is reset. Term "serial data receive" means the
per
iod
d
ur
ing wh
ich
an
8-b
it data
is
in recepti
on
, wi
th
the st
art
bit
excluded.
©
ODA
register
OD
A
7 6 5 4 3 2 0
· 1
The
registe r used to det
erm
in
e the direc
ti
on
of
the port
PA.
i-th
bil
of
the
ODA
register
When
O
PAi
is
in
th
e inp
ut
mode.
When 1
PAi is in the
out
put
mode
and
out
puts the
cont
ents
of
OP
Ai
.
DDA
can re
ad
/
wr
ite when t
he
register is selected ( 1100).
Do
not
sell this PDF !!!
71
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