Sharp PC-1500 - Page 78

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3-3-3. Pin description
(•): See Pad layout and structure in 3-5 -2 .
No. Signal Functio n No. Signal Function
name
name
1 PAl Port in put / outpu t 31 RS2
Reg
ist er se le ct i npu t
2 PA2
Po rt 1n pu l/ ou tp ul
32
RS3 Register sele ct i npu t
3
PA3 Po rt 1np uV o utpu 1
33
R/W Read/ write in put
4 PA4 Port inpuV outp ut
34
M EO
Mernory enable input
5
PA5
Po rt in put / ou tp ut
35
MEI Me r nory enable input
6 PA6
Porl in put/ ou tput
36
WO V·/ a1 t co n dit i on input
7 PA7 Port in pu l/ou l put 37
Vo/ 1 VV ait condition input
8
GNO Po \'1 er so urce 38
GND Power source
9
PBO P on in pul/ou tp u1
39
VCC P owe r so urce
10 P81 P or 1 input/ output 40 DMEO
tv 1emory ena ble out pu t
1 1 P B2
Po rt in puVou t pul 41 OMEI M emory enab le ou t pu t
12 PB3
Port inpuVou tp ul 42 WA IT Wail out put
13 P84 Po rt i npu Vou 1pu1 43 INT
Int
err upt o utp ul
14 PBS Port inpuV output
44
RESET
Initiali ze out p ut
15
P B6
Port i npuVo ulp ut 45 IRQ Interrupt in pul
16 P 87
Po rt inp uVo ulput.
Inte rrupt i npu t 46 ~ OS
Basic clock i np ut
17
P4>
P ort PC latch clock
47
cu
Se ri al re ce iv e clock i nput
18
PCO
P on output 48 S Dl Se ri al rec()ive 1np u1
19 PCl P on ou t pu 1
49
LC Nol used
20 PC2
P on outp ut
so CLO
Serial rec/ 1rn clock inpu t1ou 1put
2\ PC3 P Or' I Output 51
SDO
Serial rec/ trn i npu t/ output
22
PC4 Por t outpu t 52 DO
Oa\a
bus inp ut/out put
23 PCS Port out pu t 53
0 1 D a1 a bus i nput / outpu t
24 P C6 Por t ou tput 54
02
Oa la bus input/outp ut
25
PC7 P ort ou t pu t 55 03
Da ta bus inpu1/ou1put
26 cso
Ch ip se lect input
56
D4 Data bus inp ut / outp u1
27 CSt Ch ip se lect i nput 57
05
Da ta bus input/ outp ut
28
CS2 Ch ip sele ct i nput 58 06
D ata bus inpu t/o u tp ut
29 RSO
Register sel ec t inp ut
59
07 Data bus i nput/outpu t
30
RS l R eg ister select input
60
PAO Po rt in put / ou tput
73
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