,
92
All and more about Sharp PC-
1500
at http:/lwww.PC-1500.info
•
1
Y0
~
1Y3
is selected
by
the decoder
IC
(TC40
H1
39F)
when
the gate srignal
inpu
t
BFO
(1G)
is
low.
YO . . . .
..
With low state
of
AD
14
and
AD
15. the
YO
output goes low
so
as
to select the
(I
YO)
user memory
area
of
the module uni
t.
(A
ddr
ess assignm
ent
of
OOOQH~·
3FFF
H)
YI
. . . . . . With high state
of
AD
l4
and
low state
of
AD
15, the YI
ou
tput goes l
ow
so
as
(
TYi
) to select the
gat
e (G2A)
of
the
IC
(TC40H I 38F). (Address assignment
of
4000
H ~
7FFFH)
Y2
..
. . . . With low
sta
te
of
.
AD
14and
high
st
ate
of
AD
15, the
Y2
ou
tput goes
low
so
as
( I
Y2)
to select the
opt
ional
ROM
ar
ea
of
the
modu
le unit. (Address assignm
en
l
of
8000H~BFFFH)
Y3
....
..
With high state
of
AD
l4 a nd
AD
15
. the Y3 output goes l
ow
so
as
to selec1
(IY3) the syst
em
program
ROM
(SC6
13
28F) and the 1/ 0 port
(L
H5
8 1 I or
LH
5810). (Addre
ss
assi
gnme
nt
of
COOOH~FFFFH)
•
so
~
s7
is selected by
the
decoder·
IC
(TC40H138F)
when
the
gate s
ign
al
input
MEO
(G1)
is
high
,
Y1
(G2A) l
ow
,
and
G2B
is
l
ow
(normally
low).
SO
.
..
.
..
With all
of
AD
I I.
ADl2
and
ADl3
in low st
ate,
the
SO
outpu
t goes
low
so
as
(
YO
) to select the u
ser
RAM
(H
M6
I
16)
. (Address assignment of
400
0H
~
47
FFH)
S I
......
With hi
gh
state
of
ADI
I
and
low state
of
AD
l2
and
AD
l3. the
SI
output
(YT) goes low
so
as
to select the optional u
ser
RAM area. (A
dd
ress
as
signment
of
4
8
00H
~
4FFFH)
S2 . . . .
..
With low state
of
ADI
I
and
ADl3
and
high state
of
AD
12, the S2
ou
tput
(Y2) goes l
ow
so
as
to select the optional user RAM
ar
ea. (Address assignment
of
5000H
~
5
7FF
H)
S3 . .
...
. With low
sta
te
of
AD
11
and
AD
12
and
high state
of
AD
13,
the S3
ou
t
pu
t
(Y3) goes low
so
as
to select the user RAM
ar
e
a.
(Address assignment
of
58
00
H ~
SFFFH)
S4
..
..
. . With high state
of
ADI
I a nd
AD
l3
and
low stale of
ADl2.
the S4
ou
tput
(Y
4) goes low
so
as to select the u
ser
RAM
ar
ea. (Address
as
signment (lf
6000H
~
67FFH)
S5
...
.
..
D(l nm use.
S6
. .
...
. With low state of
AD
I I
and
high
sta
le
of
ADl2
and
ADl3.
t
he
S6
outpu
t
(Y6) g(les low
so
as
to recei
ve
on
the I/ 0 port the
data
from the display chip RAM
or
interrupt i
npu
t
fr
om
the option. (Address assignmenl
of
7CX
)()H
~
77FFH)
S7
....
. . With all
of
AD
I I,
AD
12.
a nd
AD
13
in
high stale. the S7
out
put
goes l
ow
so
(Y7) as
10
select the syslem RAM (TC55 14) (Address assignment of
7800H
~
7FFF
H
)
•
2Y2,
2Y3
is selected by
the
decoder IC (TC40H139) when t
he
2G
gate becomes
effecti
ve
after
the
selection
(low
state)
of
the TC40H138F
output
SG
(YG).
V2 .
..
...
With low st
at
e
of
AD8
and
hi
gh
st
ate
of
DM
EO.
the 2Y2 outpul goes l
ow
and
(2Y2) makes the
NANO
gate
ou
tput V2 high
so
as to select display
ch
ip I and
3.(Address assignment (lf
7600H
~76FF
H)
V3
......
With high state
of
AD8
and
DM E
O.
1h
e 2Y3
out
pu
t goes l
ow
and makes the
(2Y3)
NANO
gate
outpul
V3 hi
gh
so as
to
select d
is
pl
ay chip 2
and
4. (Ad'dre
ss
assignment of
7700H
~
77
FFH)
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