R-22GT-F
R-22GV-F
23
Pin No. Signal I/O Description
X24C02P is a 2K-bit, serial memory, enabling CMOS to be erased/written electrically. This memory is constructed with 256
registers x 8bits, enabling individual access, read and write operations to be performed. Details of input/output signal for IC2 are
as shown in the following diagram.
2-2 Memory IC (IC2)
Figure T-3 Relation between Pin Nos, and Signals
Pin No. Signal I/O Description
1-3 A0-A2 IN Connected to +5V.
4 VSS IN Connected to GND.
5 SDA IN/OUT Serial data input/output : input/outputs data to IC1.
6 SCL IN
Clock signal input : input/outputs sireal data at every one pulse.
7 TEST IN Connected to GND.
8 VCC IN Connected to +5V.
57-59 P37-P35 OUT Terminal not used.
60 P34 OUT Key strobe signal.
Signal applied to touch-key section. A pulse signal is input to P27, P26, P25 and P24 terminals
while one of G4 line keys on key matrix is touched.
61 P33 OUT
Key strobe signal.
Signal applied to touch-key section. A pulse signal is input to P27, P26, P25 and P24 terminals
while one of G5 line keys on key matrix is touched.
62 P32 OUT
Key strobe signal.
Signal applied to touch-key section. A pulse signal is input to P27, P26, P25 and P24 terminals
while one of G6 line keys on key matrix is touched.
63 P31 OUT
Key strobe signal.
Signal applied to touch-key section. A pulse signal is input to P27, P26, P25 and P24 terminals
while one of G7 line keys on key matrix is touched.
64 P30 OUT Key strobe signal.
Signal applied to touch-key section. A pulse signal is input to P27, P26, P25 and P24 terminals
while one of G8 line keys on key matrix is touched.
FUNCTIONAL DIAGRAM
E PROM
256 x 8
2
START
STOP
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER
COMPARATOR
H.V. GENERATION
TIMING
& CONTROL
64
YDEC
8
DATA REGISTER
Dout
CK
3
1
5
64
XDEC
START CYCLE
INC
LOAD
WORD
ADDRESS
COUNTER
R/W
PIN
Dout
ACK
(6) SCL
(5) SDA
(4) Vss
(3) Vcc
A0
A1
A2
VSS
VCC
TES
SCL
SDA
TOP VIEW
1
2
3
4
8
7
6
5
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