Understanding the Hardware | Hardware-Software interface
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stabilize. The output power will be within 1 dB (0.6 dB typical) of its final power within 10 microseconds,
but typically requires 5 milliseconds to stabilize to within 0.1 dB.
Please note that for ramping amplitude from low to high, 2 dB steps every millisecond for example,
the amplifier is powered on but not used for a 20 dB range, giving plenty of time for the amplifier to
fully stabilize before it is used. Also, if the amplitude is fully controlled with the I/Q data, this problem
is avoided altogether.
HARDWARE-SOFTWARE INTERFACE
Other than up-sampling by 2 or 3 on the FPGA, all digital signal processing happens on the PC. The
VSG60A software and API automatically adjust the signal amplitude, I/Q balance and DC offset to
provide an accurate, clean, flat 40 MHz modulation bandwidth. A highly optimized FIR filter on the PC
applies these corrections in real-time with minimal software overhead.
An array of correction constants across frequency and temperature is generated by running each
VSG60A through an environmental chamber and storing this data to internal flash memory.
A state machine inside the FPGA processes I/Q data, triggers, frequency steps, and amplitude steps.
This allows precise timing relationships between events such as frequency hops.
OPTIMIZING PERFORMANCE
Pulse Modulation
When using our user interface software, the “off” state can be optimized by changing the I/Q offset to
minimize the LO feed-through until a spectrum analyzer, such as the SM200A, reads a minimum
amplitude. Typically, 60 dB on/off ratio is possible using this method.
When using the API, two additional tricks are available. If the pulse will be sent to a receiver with 20
MHz bandwidth or less, converting the pulse to a 15-16 MHz offset tone will place the LO feed-through
in the “off” state outside the 20 MHz bandwidth.
Spurious
The VSG60A uses a fractional-N synthesizer. If your application allows for some flexibility in frequency
selection, sticking to even multiples of 4, 5, or 10 MHz for your center frequency will reduce or
eliminate fractional-N spurs.
Bandwidth
For a 50 MSPS sample rate, digital filters in the FPGA begin to roll off just past an 18 MHz offset, and
are down about 1 dB by 20 MHz offset from center. By keeping signal bandwidth to 72% or less of
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