Silicon Laboratories Si4010-C2 - Page 2

Silicon Laboratories Si4010-C2

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Si4010-C2

2 Rev. 1.0

Functional Block Diagram

Si4010

NVM

8 Kbyte

EEPROM

128-bit

VDD

GND

PA

RAM/

ROM

PUSH

BUTTONS

CR2032

COIN CELL

1.8 – 3.6 V

DIVIDER

I/O

INTERFACE

GPIO

4/8

INTEGRATED 8051 MCU

LDO REGULATOR

TXM

TXP

LOOP

ANTENNA

FSK OOK

LED

VDD

Table of Contents

Default Chapter3
- Table of Contents3
1 System Overview11
- Figure 1.1. Si4010 Block Diagram12
2 Test Circuit13
- Figure 2.1. Test Block Diagram with 10-Pin MSOP13
3 Typical Application Schematic14
- Si4010 Used in a 5-Button RKE System with LED Indicator14
- Si4010 with an External Crystal in a 4-Button RKE System with LED Indicator14
- Figure 3.1. Si4010 Used in a 5-Button RKE System with LED Indicator14
- Figure 3.2. Si4010 with an External Crystal in a 4-Button RKE System with LED Indicator14
4 Ordering Information15
- Table 4.1. Product Selection Guide15
5 Top Markings16
- Soic16
- Figure 1. Si4010 Top Marking16
- Table 1. Top Marking Explanation16
- Msop17
- Figure 2. Si4010 Top Marking17
- Table 2. Top Marking Explanation17
6 Pin Definitions18
- MSOP, Application18
- MSOP, Programming/Debug Mode19
- SOIC Package, Application20
- SOIC Package, Programming/Debug Mode21
7 Package Specifications22
- 10-Pin MSOP22
- Figure 7.1. 10-Pin MSOP Package22
- Table 7.1. Package Dimensions22
- 14-Pin SOIC Package23
- Figure 7.2. 14-Pin SOIC Package23
- Table 7.2. Package Dimensions23
8 PCB Land Pattern 10-Pin MSOP24
- Figure 8.1. 10-Pin MSOP Recommended PCB Land Pattern24
- Table 8.1. 10-Pin MSOP Dimensions25
9 PCB Land Pattern 14-Pin SOIC Package26
- Figure 9.1. 14-Pin SOIC Recommended PCB Land Pattern26
- Table 9.1. PCB Land Pattern Dimensions27
10 Electrical Characteristics28
- Table 10.1. Recommended Operating Conditions28
- Table 10.2. Absolute Maximum Ratings28
- Table 10.3. DC Characteristics29
- Table 10.4. Si4010 RF Transmitter Characteristics30
- Table 10.5. Low Battery Detector Characteristics31
- Table 10.6. Optional Crystal Oscillator Characteristics31
- Table 10.7. EEPROM Characteristics32
- Table 10.8. Low Power Oscillator Characteristics32
- Table 10.9. Sleep Timer Characteristics32
11 System Description33
- Overview33
- Figure 11.1. Functional Block Diagram33
- Setting Basic Si4010 Transmit Parameters35
- Applications Programming Interface (API) Commands35
12 Power Amplifier36
- Figure 12.1. Simplified PA Block Diagram36
  - Register Description38
- SFR Definition 12.1. PA_LVL38
- XREG Definition 12.3. Bpa_Trim39
13 Output Data Serializer (ODS)40
- Description40
- Timing40
- Figure 13.1. OOK Timing Example40
- Figure 13.2. FSK Timing Example40
- Register Description41
- SFR Definition 13.1. ODS_CTRL41
- SFR Definition 13.2. ODS_TIMING42
- SFR Definition 13.3. ODS_DATA43
- SFR Definition 13.4. ODS_RATEL43
- SFR Definition 13.5. ODS_RATEH44
- SFR Definition 13.6. ODS_WARM144
- SFR Definition 13.7. ODS_WARM245
14 LC Oscillator (LCOSC)46
- Register Description46
- SFR Definition 14.1. LC_FSK46
15 Low Power Oscillator and System Clock Generator47
- Register Description47
- SFR Definition 15.2. SYSGEN48
16 Crystal Oscillator (XO)49
- Register Description49
17 Frequency Counter50
- Figure 17.1. Frequency Counter Block Diagram50
  - Register Description52
- SFR Definition 17.1. FC_CTRL52
- SFR Definition 17.2. FC_INTERVAL53
- XREG Definition 17.3. IFC_COUNT53
18 Sleep Timer54
19 Bandgap and LDO54
20 Low Leakage HVRAM54
21 Temperature Sensor54
22 Microcontroller55
- Figure 22.1. CIP-51 Block Diagram55
- SFR Definition 22.1. DPL61
- SFR Definition 22.2. DPH61
- SFR Definition 22.3. SP62
- SFR Definition 22.4. ACC62
- SFR Definition 22.5. B63
- SFR Definition 22.6. PSW64
23 Memory Organization65
- Figure 23.1. Address Space Map after the Boot65
24 System Boot and NVM Programming69
- Startup Overview69
- Reset70
- Chip Program Levels70
- NVM Organization71
- Device Boot Process72
- Figure 24.1. NVM Address Map72
- Error Handling During Boot73
- CODE/XDATA RAM Address Map73
- Figure 24.2. CODE/XDATA RAM Address Map75
- Boot Status Variables76
- Table 24.1. Boot XDATA Status Variables76
- SFR Definition 24.2. BOOT_FLAGS78
- NVM Byte Definition 24.3. PROT3_CTRL83
  - Chip Protection Control Register84
- SFR Definition 24.4. PROT0_CTRL84
25 On-Chip Registers85
- Special Function Registers85
- Table 25.1. Special Function Register (SFR) Memory Map85
- Table 25.2. Special Function Registers86
- XREG Registers88
- Table 25.3. XREG Register Memory Map in External Memory89
- Table 25.4. XREG Registers90
26 Interrupts91
- MCU Interrupt Sources and Vectors92
- Interrupt Priorities92
- Interrupt Latency92
- Interrupt Register Descriptions93
- Table 26.1. Interrupt Summary93
- SFR Definition 26.1. IE94
- SFR Definition 26.2. IP95
- SFR Definition 26.3. EIE196
- SFR Definition 26.4. EIP197
- SFR Definition 26.5. INT_FLAGS98
  - External Interrupts99
- SFR Definition 26.6. PORT_INTCFG100
27 Power Management Modes101
- Idle Mode101
- Stop Mode101
- SFR Definition 27.1. PCON102
28 AES Hardware Accelerator103
- AES SFR Registers103
- SFR Definition 28.1. GFM_DATA104
- SFR Definition 28.2. GFM_CONST104
- SFR Definition 28.3. SBOX_DATA105
- SFR Definition 28.4. SYS_SET105
29 Reset Sources106
- Device Boot Outline106
- External Reset106
- Software Reset107
30 Port Input/Output108
- Figure 30.1. Device Package and Port Assignments108
- SFR Definition 30.1. P0118
- SFR Definition 30.2. P0CON119
- SFR Definition 30.3. P1119
- SFR Definition 30.4. P1CON120
- SFR Definition 30.5. P2120
- SFR Definition 30.6. PORT_CTRL121
- SFR Definition 30.7. PORT_SET122
31 Clock Output Generation123
- Figure 31.1. Output Clock Generator Block Diagram123
  - Register Description124
- SFR Definition 31.1. CLKOUT_SET124
32 Control and System Setting Registers126
- SFR Definition 32.1. GPR_CTRL126
- SFR Definition 32.2. GPR_DATA126
- SFR Definition 32.3. RBIT_DATA127
33 Real Time Clock Timer128
- Figure 33.1. RTC Timer Block Diagram128
  - RTC Interrupt Flag Time Uniformity129
  - Register Description129
- SFR Definition 33.1. RTC_CTRL130
34 Timers 2 and 3131
- Interrupt Flag Generation132
- Figure 34.1. Timer Interrupt Generation132
- 16-Bit Timer with Auto Reload (Wide Mode)133
- 16-Bit Capture Mode (Wide Mode)133
- Figure 34.2. Timer 16-Bit Mode Block Diagram (Wide Mode)133
- 8-Bit Timer/Timer Mode (Split Mode)134
- Figure 34.3. Capture 16-Bit Mode Block Diagram (Wide Mode)134
- 8-Bit Capture/Capture Mode (Split Mode)135
- Figure 34.4. Two 8-Bit Timers in Timer/Timer Configuration (Split Mode)135
- 8-Bit Timer/Capture Mode (Split Mode)136
- Figure 34.5. Two 8-Bit Timers in Capture/Capture Configuration (Split Mode)136
- Figure 34.6. Two 8-Bit Timers in Timer/Capture Configuration (Split Mode)137
- Figure 34.7. Two 8-Bit Timers in Capture/Timer Configuration (Split Mode)138
- SFR Definition 34.1. TMR_CLKSEL139
- SFR Definition 34.2. TMR2CTRL140
- SFR Definition 34.3. TMR2RL142
- SFR Definition 34.4. TMR2RH142
- SFR Definition 34.5. TMR2L143
- SFR Definition 34.6. TMR2H143
- SFR Definition 34.7. TMR3CTRL144
- SFR Definition 34.8. TMR3RL146
- SFR Definition 34.9. TMR3RH146
- SFR Definition 34.10. TMR3L147
- SFR Definition 34.11. TMR3H147
35 C2 Interface148
- C2 Pin Sharing148
- Figure 35.1. 10-Pin C2 USB Debugging Adapter Connection to Device148
- Figure 35.2. 14-Pin C2 Toolstick Connection to Device150
36 IDE Development Environment and Debugging Chain151
- Functionality Limitations While Using IDE Development Environment151
- Chip Shutdown Limitation152
- LED Driver Usage While Using IDE Debugging Chain152
37 Additional Reference Resources154
Document Change List155
Contact Information156

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