SMSL SU-6 - DPLL Clock Jitter Control; Display Brightness Levels

Instructions
DPLL
DPLL 1-9, the smaller the number, the better the performance against clock jitter.
LEVEL 1~ LEVEL 5
BRIGHTNESS
This DPLL setting is a special function of ESS series products. It can adjust the internal
DPLL digital phase locked loop circuit Bandwidth, so that the chip achieves a balance
between anti clock jitter and input tolerance.
Its function:
When the clock stability of the input signal is good, this value can be reduced,
so that the clock performance of the system is better;
When the clock stability of the input signal is not good, the sound may be inter-
rupted. Increase this value can avoid the sound interruption! Especially when
using TV as signal source!