Sony CDP-211 - Page 9

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Pin Name
LRCK
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45
DA 09 output when PSSL=1. XPLCK output when PSSL=0
47 BCLK
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1
52
64LRCK
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DA 08 output when PSSL=1. GFS output when PSSL=0
DA 07 output when PSSL=1. RFCK output when PSSL =0
55 =
DA 06 output when PSSL=1. C2PO output when PSSL=0
PFCK
C2PO
XRAOF
MNT3
MNT2
MNT1
MNTO
XTAI
XTAO
~XTSL
57
8
59
|
4,2336MHz
output
o
61
62
63
es
FSTI
FSTO
C4M
C16M
D
DOUT
EMPH
WFCK
SCOR
SBSO
EXCK
SUBQ
SQCK
MUTE
SENS
XRST
DIRC
SCLK
DFSW
ATSK
DATA
XLAT
CLOK
67
[ep] Oo
Go =
70
71
72
3
74
75
76
TT
78
79
= SS
~)
Clock input for SBSO read-out
Sub-Q 80-bit output
81
82
83
84
85
Used in 1-track jump mode
DFCT selection pin
Input pin for anti-shock
Serial data input, supplied from CPU
Latch input, supplied from CPU
Serial data transfer clock input, supplied from CPU
SENS serial data read-out clock
87
88
Clock input for SQSO read-out