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Sony CDP-561 - Section 5: Printed Wiring Board Diagrams (BD); BD Board Component Layout

Sony CDP-561
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5-4.
SCHEMATIC
DIAGRAM
BD
SECTION
¢
See
page
8
for
IC
Pin
Function.
(IC101)
ps
of
a
LAON
WM
11
12
13
A,
OPTICAL
PICK-UP
(KSo=2
LSBAAEHN)
2
ol—)
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ES!
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FCS
COIL
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[B+]
{BD
BOARD)
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4IN
BOARD
CN3Of
*
Signal
path,
TRK
COIL
2
AXIS
mcm
2ars
|
e>
0
ZZ>>
digital
out
NOTE
e
All
capacitors
are
in
#F
unless
otherwise
noted.
pr:
gpF
SOW
or
less
are
not
indicated
except
for
electrolytics
and
tantalums,
*All
resistors
are
in
Q
and
1/4W
or
less
unless
otherwise
specified,
Note:The
components
identified
by
mark
ANor
dotted
line
with
mark
AXare
critical
for
safety,
Replace
only
with
parf
number
specified,
«
[B+]
:Bt
Line.
«Voltages
and
waveforms
are
de
with
respect
to
ground
under
no-Signa!l
conditions,
no
mark:SIQP
«Voltages
are
taken
with
a
VOM(Input
impedance
10MQ).
Voltage
variations
may
be
noted
due
to
norma!
produc-
tion
tolerances,
e
Waveforms
are
taken
with
a
oscilloscope.
Voltage
variations
may
be
noted
due
to
norma!
produc-
tion
tolerances,
*Circled
numbers
refer
to
waveforms,
e
Waveformes
WIR
\)
4
YY
X)
ANY
YY)
Wy
'
|
AW
viata
WY
APPROX
500mVp-p
IC101
@)
PLAY
@
TMU.
2
sy
ALT
TTT
APPROX
200mVp-p
IC101
PLAY
®
2.6Vp-p
ian
©
7.5
usec
nae
ina
as
IC101
PLAY
IC102
BA6392FP
qa
CAPA
IN
1
CHi
RIN
BUFF
oO
wo,
VY
sia
INTERFACE
oO
°
CH!
F
IN
VREF
IN
(6)
S
>
Fc
aall
VREF
OUT
(7)
GNO
(8)
CH2
F
IN
(3)
2
[a
_[intenrace
CH2
R
IN
CAPA
IN
2
oe,
QF
(>)
cH2
out
F
(3)—<]
©
GND
(14)
|
>—G@)
cHe
ouT
F
>
CH4
OUT
R
F
(20)
CH3
F
IN
inreneace|
CHS
RIN
(18)
CAPA
IN
3
BUFF
>of
>
{7
cH3
OUT
R
BUFF
(16)
CH3 OUT
F
(15)
MUTE
-
iC
Block
Diagrams
IC101
CXD2545Q
i
XTAl
XTAO
(5)
VPCO
Oo
st
ar
im 3)
pr
wn
_
oOo
we
x<
>
CNEIEHES-“2D
CLOCK
\
|
GENERATOR
DIGITAL
PLL
[
o<
cp
wa
ro
m
D
wo
BA
mo
moa
ede
©
m
=x
35
om en
c=
>
a
So
B
RESISTER
ae
>=
orotetson
e—____reisee
|
leeeless
=
SSOR
PROC
@y
NOI
18-TIMES
|
HOLS,
OVERSAMPL
ING;
FILTER
CONVERTER
BUFF.
MIRR
FCT
FOK
SETE
CLV
PROCESSOR
32K
RAM
ADRESS
GENERATOR
ERROR
CORRECTOR
ee
Eee
ee
CTOR
ee
(2)
FOK
PRIORITY
ENCOBER
PROCESSOR
i
oe
D/A
(——1oata
processor
SERVO
9
SEQUENCER
EBnS
‘AM
|
ERAGE
ae
oe
ee
pre
ee
CDP-561/561E
PSSL
Al
PARALLEL
I-40)
ba01-16
MUTE
PEAK
DETECTOR
MAZ
oe
eee
CPU
INTERFACE
ee
CLOK
XLAT
)
OUT
SENS
SRON,
SROR
TFDR,
TFON
TRON,
TROAR
FFOAR,
FFON
FRON,
FROR

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