Sony CDP-561 - Section 5: Schematic Diagrams (BD); BD Board Circuit Schematics

NOTE
* All copacitors are in uf unless otherwise noted, pF:uuF ® Waveformes
SOW or fess are not indicated except for electrolytics
and tontaluas,
*All resistors are in Q and 1/4W or fess unless otherwise
specified.
° 4 :internal component,
° [__] :Panel designation,
Note:The components identified by mark AN or dotted
tine with mark AN ore critical for safety.
Replace onty with port number specified.
¢ {Bt} :Bt Line.
¢ [B=] :B- Line.
¢ Voltages and waveforms are dc with respect to ground
under
no-signal
Geturned)
conditions,
——e}—__1~—
0.48
—o}—_}—
.48
nsec
1.
no
mark:
STOP
ais
‘
)
LOnD
aut
IC303
@
IC801
PLAY
iL
h
°
*
Voltages
cre
iaken
with
o
YOM
(Input
impedance
10MG)
@)
Voltage
variations
may
be
noted
due
to
normal
producm
tion toleronces,
eWoveforms are token with c oscilloscope,
Voltage variations may be noted due te hormal produc-
tion
toleronces,
—>}+—_}«—_
23
usec
*Circled
numbers
refer
to
waveforns,
IC303
@
«Signal
path,
zzp> (0
ZZp> :figital out
¢ IC Block Diagrams
IC301 LB1641
Rake
5.3Vp-p
oa
IC920 M51957AL
oc
=. e
oO Q 9
oh S 5 eee Le aa Ba =u - bt =
4 22 2 888 2 258 ee¥ zg &zr &
= 236 fo eae tr 2 3 a? @ i = SH=ae G
XSEL
20/ 16
"O° DETECT
MUTE
MUTEL (i) CIRCUIT G0) SPLK
TEST! G3) OFVoat
(28) aVEDR
TEST2 G) Gi) evssa
BFVOD2
(26)
vSuB
(C)
R
avaaL G6) wae
AVSSL G7) @) veo
VSUB (C) L Ge)
VOHP2
vaa
(60)
(23)
RI
(-)
vss
LA (+)
vss @2)
L1 (4) 63) <] 3rd order whe AC. BC 3rd order (21) RI @)
NOISE NOISE.
SHAPER QITHER SHAPER
vss2 (8) cLock @0) vss2
GENERATOR
O-D-O-O) OOO (D119 -1)-19) WALDO
xy oO a nN 2 @ b z on on x NN ~~ oO
o FF G FT ae 86 OW @ 2 = 9 OD +. GQ @& TH EH
ee a oe 2s Be Se BAe rms
= 4 Es ES fo c
8 g
5.6Vp-p
v
45.1584 MHz —=}-—_+_ 0.18 psec
1C303 ©) IC303
. Fer ul
ak hs
CDP-561/561E
5-6. PRINTED WIRING BOARD — MAIN SECTION —
¢ See page 12 for Circuit Boards Location.
“semiconductor [T] [2 «| 3+ 4+ ~5 | 6 | 7 | 8 oo se i eo
[Ret no. [Lovato
G-6
J301
{TRANSFORMER
BOARD]
_
A
[LANE
OUT]
VARIABLE
|
{SW
BOARD]
1C305
— [MAIN BOARD] ‘emi ne
Oc ® @
(MVR BOARD]
TTMm aT
an
moOO BPO
OM
[o>]
0 1) cn ©
[LOADING BOARD]
(CHASSIS)
& oO
B
B
C-
Cc
(CHASSIS)
IOV
oa a oe
On
nh
i
an +
ODO
(CHASSIS)
!
a
ayn
ox) or
fd )
Mm
{DISP BOARD]
x= _
o
a
on
NOT REPLACEABLE BUILT IN TRANSFORMER
2099 abapan
Pe hb
a
$820 $82! VA
[Timel /
bee4
shies
'-655-759-
o9
:
pN BD BOARD CNIO!
Note:
¢ o— — : parts extracted from the components side.
* ot. : Denotes that Jumper wire works as Test Point.
: : Pattern from the side which enable seeing.
—
22
—
=
23
—
24
—