Sony CDP-561 - RF PLL Frequency Verification; Circuit Board Adjustment Locations

RF PLL Free-run Frequency Check
Procedure :
1. Connect frequency counter to test point (PLCK) with lead
wire.
frequency counter
ae
TP(PLCK) o«———o +
2. Turned Power switch on.
3. Put the disc (YEDS-18) in to play the number five track.
Confirm that reading on frequency counter is 4.3218MHz.
Main board
anne
Adjustment Location :
[ MAIN BOARD ] — Component Side —
fo TP (ADJ)
[ BD BOARD J] — SIDE A—
1C103| (RF) (FEI)
See al? site)
re}
°
(VC)
fe)
(PLCK)