Sony CDX-T67 - Page 31

31
CDX-T67
Pin No. Pin Name I/O Description
47, 48 MD0, MD1 I Setting terminal for the CPU operational mode (fixed at “H” in this set)
49 MD2 I Setting terminal for the CPU operational mode (fixed at “L” in this set)
50 EJECT SW I Eject switch (SW303) input terminal “L” active
51 MAGLK SW I
Magazine in/out detect switch (SW302) input terminal
“L”: magazine in/out operation, “H”: normally
52 SCOR I Subcode sync (S0+S1) detection signal input from the CXD3017Q (IC401)
53 GRSCOR I Subcode sync (S0+S1) detection signal input terminal Not used (open)
54 NC O Not used (open)
55 HS O
Normal/high speed playback control signal output terminal
“L”: high speed playback Not used (open)
56 SQSO I Subcode Q data input from the CXD3017Q (IC401)
57 NC O Not used (open)
58 SQCK O Subcode Q data reading clock signal output to the CXD3017Q (IC401)
59 CDCLK O Serial data transfer clock signal output to the CXD3017Q (IC401)
60 CDLAT O Serial data latch pulse signal output to the CXD3017Q (IC401)
61 CDDAT O Serial data output to the CXD3017Q (IC401)
62 XRST O System reset signal output to the CXD3017Q (IC401) “L”: reset
63 XQOK O Subcode Q OK pulse signal output terminal Not used (open)
64 XRDE O D-RAM read enable signal output terminal Not used (open)
65 XWRE O D-RAM write enable signal output terminal Not used (open)
66 EMPH O Emphasis control signal output to the CXD3017Q (IC401) “H”: emphasis on
67 MUTE O Audio line muting on/off control signal output “H”: muting on
68 RAMA10 O Address signal output to the S-RAM Not used (open)
69 RAMCS O Chip select enable output to the S-RAM Not used (open)
70 to 74
RAMIO7 to
RAMIO3
I/O Two-way data bus with the S-RAM Not used (open)
75 RESET I
System reset signal input from the SONY bus interface (IC201) and reset signal generator (IC204)
“L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
76 RAMIO2 I/O Two-way data bus with the S-RAM Not used (open)
77 X1A O Sub system clock output terminal Not used (open)
78 X0A I Sub system clock input terminal Not used (fixed at “L”)
79 VSS — Ground terminal
80 X0 I Main system clock input terminal (4 MHz)
81 X1 O Main system clock output terminal (4 MHz)
82 VCC — Power supply terminal
83, 84
RAMIO1, RAMIO0
I/O Two-way data bus with the S-RAM Not used (open)
85 to 88
RAMA0 to RAMA3
O Address signal output to the S-RAM Not used (open)
89 SINGLE I
Setting terminal for the single disc/multiple discs mode
“L”: single disc mode, “H”: multiple discs mode (fixed at “H”)
90 6/10 SEL I
Setting terminal for the 6 discs changer/10 discs changer model
“L”: 10 discs changer model, “H”: 6 discs changer model (fixed at “H”)
91 CFSEL I Custom file on/off setting terminal “L”: custom file on Not used (fixed at “H”)
92 TEXTSEL I
CD text mode setting terminal
“L”: CD text on, “H”: does not display track name Not used (fixed at “H”)
93 ESPSEL I ESP mode setting terminal “L”: ESP on Not used (fixed at “H”)
94 TEST I Test on/off setting terminal “L”: test mode Not used (fixed at “H”)
95 MAG SW I Magazine detect switch (SW301) input terminal “L”: magazine is set