Sony CFD-E100WHITE - Page 43

43
CFD-E100/E100L
• IC Pin Function Description
MAIN BOARD IC801 µPD789478GC-A41-8BT-A (SYSTEM CONTROLLER)
Pin No. Pin Name I/O Description
1, 2
NC - Not used
3 to 5
VLC2 to VLC0 - Terminal for doubler circuit capacitor connection to develop liquid crystal display drive voltage
6 to 9
COM0 to COM3 O Common drive signal output to the liquid crystal display
10 to 26
S0 to S16 O Segment drive signal output to the liquid crystal display
27
REC I
Recording/playback detection signal input terminal
"L": playback mode, "H": recording mode
28
AC-CHK I AC voltage detection signal input terminal "L": AC IN
29 CD DOOR I
CD lid close detection switch input terminal "L": close
30 to 34
NC - Not used
35
A-MUTE O Audio muting on/off control signal output terminal "H": muting on
36 CD O
CD function control signal output terminal "H": CD on
37 TAPE O
Tape function control signal output terminal "H": tape on
38
AVDD - Power supply terminal (+3.3V)
39
NC - Not used
40
CD6V-CHK
I
Power supply voltage (+6V) for CD block monitoring terminal
41 6V-CHK I
Power supply voltage (+6V) monitoring terminal
42 3V-CHK I
Power supply voltage (+3V) monitoring terminal
43 9V-CHK I
Power supply voltage (+9V) monitoring terminal
44, 45 KEY2, KEY1 I
Front panel key input terminal (A/D input)
46 MODE CHK
I Model destination setting terminal
47
AGND - Ground terminal
48 REMOTE I
Remote control signal input from the remote control receiver
49
TC-PLAY I Tape play detection switch input terminal "L": tape play mode
50
WP/INI I/O
Interrupt status input terminal
Output terminal for wake up/Initial reset signal reading
51 NC
- Not used
52
C-WRQ I Interruption detection signal input from the digital signal processor
53
C-DOUT I Serial data input from the digital signal processor
54
C-DIN O Serial data output to the digital signal processor
55
C-CLK O Serial data transfer clock signal output to the digital signal processor
56
C-DRF I Focus on/off detection signal input from the digital signal processor
57
C-CE O Chip enable signal output to the digital signal processor
58
C-FSEQ I Synchronizing signal detection signal input from the digital signal processor
59
C-XRT O System reset signal output to the digital signal processor "L": reset
60 P-CON O
Power on/off control signal output terminal "L": standby mode, "H": power on
61
R-COUNT I PLL serial count data input from the FM/AM PLL
62
R-DATA O PLL serial data output to the FM/AM PLL
63
R-CLK O PLL serial data transfer clock signal output to the FM/AM PLL
64
R-LAT O PLL chip enable signal output to the FM/AM PLL
65
R-MUTE O Tuner muting on/off control signal output to the FM/AM PLL "H": muting on
66
ISS1 O ISS 1 on/off control signal output terminal "H": ISS 1 on
67
ISS2 O ISS 2 on/off control signal output terminal "H": ISS 2 on
68
M-BASS O MEGA BASS on/off control signal output terminal "L": MEGA BASS on
69
IC0 I Not used
70 XT1 I
Sub system clock input terminal (32.768 kHz)
Ver. 1.1