44
CFD-E100/E100L
Pin No. Pin Name I/O
Description
71 XT2 O
Sub system clock output terminal (32.768 kHz)
72
VDD - Power supply terminal (+3.3V)
73
VSS - Ground terminal
74
X1 I Main system clock input terminal (4.19 MHz)
75
X2 O Main system clock output terminal (4.19 MHz)
76
RST I
System reset signal input "L": reset
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
77 V-CLK O
Serial data transfer clock signal output to the electrical volume
78 V-DATA O
Serial data output to the electrical volume
79 SCL O
Serial data transfer clock signal output to EEPROM
80
SDA I/O Two-way data bus with the EEPROM
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