Sony D-E666 - Page 10

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D-E666/EJ620/EJ621/EJ622/EJ623/EJ625/EJ626CK
Pin No. Pin name I/O Description
41 BATDET I Battery detection input.
42 XHGOM O Optical pick-up power ON/OFF control signal output terminal. “L”: ON
43 XLAT O Serial data latch pulse signal output to IC601.
44 XSOE O Serial data output enable signal output terminal.
45 RESERVE — Not used ( Fixed at “H”).
46 XPOWLT O Latch signal output to the power control (IC401).
47 RESERVE — Not used (Fixed at “H”).
48 XAPC OFF O APC mute signal output terminal. “L”: mute
49 SEG15 — Not used (open).
50 to 64 SEG14 to SEG0 O Segment drive signal output to the liquid crystal display.
65 to 68 COM3 to COM0 O Common drive signal output to the liquid crystal display.
69 to 71 V3 to V1 O Bias signal output to the liquid crystal display driver.
72, 73 C1, C0 O Capacitor connected terminal for the liquid crystal display driver voltage-up.
74 STOP O VCD control stop signal output terminal. Not used (Fixed at “L”).
75 TEST I Test terminal for IC (Fixed at “L”).
76 XVCC2SD O VCC2 voltage control signal output terminal.
77 XLED O LCD back light control signal output to the liquid crystal display. (EJ616CK)
System reset signal input from the power control (IC401). “L”: reset
78 RESET I For several hundreds msec. after the power supply rises, “L” is input, then it changes to
“H”
79 XIN I System clock input terminal.
80 XOUT — Not used (OPEN).