DCR-IP1/IP1E
3. BLOCK DIAGRAMS
3. BLOCK DIAGRAMS
A1 LK – A3 LK
A1 LK – A22 LK
A1 LK – A19 LK
MPEG
VIDEO/AUDIO
CODEC, SDRAM
(5/18)
MUX/DEMUX,
MPEG STREAM
CONTROL
(6/18)
i LINK
INTERFACE
(8/18)
X601
24.576MHz
RYI0 DE0 – RYI3 DE3
Y1
V2
U4
U2
RCI0 DE4 – RCI3 DE7
HADR
[
0
]
–
[
13
]
HADR
[
0
]
–
[
11
]
ED0 – 7
W1
V1
T2
U1
N1
RYO0 DEHD
M4
RYO1 DEVD
N5
RYO2 DEFLD
V4
RCO0 EDHD
AA1
RCO1 EDVD
Y2
RCO2 EDFLD
AD4 Y4 AA5
AC5 AD5 AC6
AD6 AD7
M23 M20 M24
N21 N24
P21 P20 P24
R21 R23 R24
T21 T24
U21 U20 U24
ADATAOUT0
ADATAIN0
SFD BCK
SFD LRCK
D0 LK – D15 LK
D0 LK – D15 LK
A12 D12 A11 D11
Y9 D10 C10 AD9
BS
[
0
]
–
[
7
]
AA8
BCK
D4 A4 D6 A5
B6 A6 D8 A7
L16 K15 K17 J17
J15 H14 J16 H15
HDAT
[
0
]
–
[
7
]
HDAT
[
0
]
–
[
7
]
HADR
[
0
]
–
[
11
]
HADR
[
0
]
–
[
13
]
HDAT
[
0
]
–
[
7
]
HDAT
[
0
]
–
[
7
]
TPA, NTPA,
TPB, NTPB
BSD IN, BSD OUT
K2 J4 J1 J2
H1 J5 G1 G2
F4 F1 F2 E1
F5 E2
D17 E16 E14 E15
C17 D16 D14 B17
B15 A15 C14 D13
A14
Y21
B21
A3
B4
AENCD, AEDE
ADDRESS BUS
A23
A24
C6
B5
ADECD, ADDE
B21
ABCK
D14
MPLCK27
D5
Y23
DSCK LK
B11 D9 B10 A9
D8 A8 B9 C8
A13
DSCK LK
C13
MPLCK27
G16
RCO2 EDFLD
B16
HYI PLL27IN
CTRL1
RECA1
REFSWP
RYO3 SGOUT
F14
SWP
F17
REF SWP
SWP
REF SWP
ENC XDEC
L15
XREC ACT M
M16
XREC ACT P
PB PWRTRNS ON
D4
C2 C1 E4 E3
D1 D2 F3 E2
IC601DT
[
0
]
–
[
7
]
M17
L14
T5
R2
R3
RECA2
U5 55
PB DATA
J12
47
RECCLK
R6 57
RECDT
P6 61
51
52
49
IC1101 MODE
SW PS
RECA1
56 59
REC/PB AMP
(7/18)
PB POWER
TRANS
(14/18)
REC M/E
37
PB IN
50
3
39
Q1101,
1103
Q1102,
1104
11
15
6
1
10
6
5
9
8
1
2
CN102
REC P/E
REC M/S
REC P/S
RW+, RW–
USB CONTROL,
MS INTERFACE
(9/18)
(1/2)
77 – 79
81 – 85
65 – 67
69 – 71
73 74
51 – 56
58 59
61 – 64
87
136
ı
139
150
149
DATA BUS
2
CPC
(FOR CHECK)
3
4
6
RF OUT
CN107
(NO MOUNT)
SWP
5
RAW PBH
7
MD2
8
XCS MC FLASH
14
MTM TRG0
15
MTM TRG1
DRUM
MCH REC HEAD
PCH REC HEAD
MCH PB HEAD
(MR HEAD)
PCH PB HEAD
(MR HEAD)
V20
U23
V21
VC-333 BOARD (3/6)
32M bit
FLASH
MEMORY
(10/18)
29 – 36
38 – 45
1 – 10 13
16 – 25 48
D0 LK – D15 LK
ADDRESS BUS
DATA BUS
187
110
39 41 – 45
47 49 51
52 54
56 – 60
61 – 64 66
68 – 70 72
73 75 76 78
79 81 83 – 88
90 92
184
X901
48MHz
2
4 2
4
1
(9/18)
(9/18)
A0 LK – A22 LK
D0 LK – D15 LK
A0 LK – A22 LK
D0 LK – D15 LK
DSCK LK
SFD LRCK
238
239
USB CLK
05
AD22
146
138
XWAIT
LXWAIT
215
214
213
E17
OVERALL (4/6)
(PAGE 3-7)
18
OVERALL (4/6)
(PAGE 3-7)
27
OVERALL (4/6)
(PAGE 3-7)
16
OVERALL (2/6)
(PAGE 3-3)
8
OVERALL (2/6)
(PAGE 3-3)
7
OVERALL (5/6)
(PAGE 3-9)
15
OVERALL (2/6)
(PAGE 3-3)
9
OVERALL (5/6)
(PAGE 3-9)
25
OVERALL (4/6)
(PAGE 3-7)
17
P16
M14
N15
MIC SO, SI, SCK
OVERALL (6/6)
(PAGE 3-12)
24
QTM1
QTM2
QTM1
QTM2
A : VIDEO SIGNAL
A : VIDEO/AUDIO SIGNAL
A : VIDEO/AUDIO/SERVO SIGNAL
A : AUDIO SIGNAL
11
10
12
EEP SO, EEP SI, EP SCK
OVERALL (5/6)
(PAGE 3-9)
31
OVERALL (2/6)
(PAGE 3-3)
10
IC701
IC801
IC601
IC905
IC907
IC903
IC904
IC1101
IC1301
MS DIO, MS BS, MS SCLKMS DIO, MS BS, MS SCLK
USB D±
USB D±
MCH PB
HEAD AMP
PCH PB
HEAD AMP
SWP
POWER
5
11
11
AC21
AC22
AA19
3-5 3-6
3-3. OVERALL BLOCK DIAGRAM (3/6)
( ) : Number in parenthesis ( ) indicates the division number of schematic diagram where the component is located.
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