Sony DCR-IP1 - Page 45

DCR-IP1/IP1E
NO MARK:REC/PB MODE
2.8
4.9
3.1
MS MS
MS MS
MS MS
MS MS
MS MS
MS MS
LN2901
CHASSIS_GND
S2901
39PCN2902
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
29P
CN2903
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
C2903
0.1u
R2904
XX
1u
C2902
C2901
1u
01ZA8.2(TPL3)
D2904
01ZA8.2(TPL3)
D2903
1500
R2903
01ZA8.2(TPL3)
D2902
6P
CN2901
1
2
3
4
5
6
2200
R2902
CN2905
12P
1
GND
2
BS
3
VCC
4DIO
5
N.C.
6
INS
7
N.C.
8
SCLK
9
VCC
10
GND
8PCN2904
1
2
3
4
5
6
7
8
01ZA8.2(TPL3)
D2905
NJU7241F31(TE2)
IC2901
123
45
1k
R2905
VD2901
R2906
100k
R2907
100k
R2908
100k
R2909
100k
0
R2911
0.1u
C2904
FB2901
FB2902
1
A
SCLK
MS_VCC_ON
REG_GND
DISPLAY
INS
SP-
XSYS_RST(N.C.)
BS
PANEL_OPEN_SW
SP+
LI_3V
DIO
REG_GND
RESET_SW
RESET
REG_GND
PANEL_G
TP_Y
REG_GND
PANEL_VD
REG_GND
TP_X
TP_SEL1
PANEL_R
PANEL_HD
REG_GND
REG_GND
PANEL_B
BL_CONT
PANEL_REVERSE
XSYS_RST(N.C.)
REG_GND
BL_-V
PANEL_HD
PANEL_VD
PANEL_G
PANEL_R
PANEL_B
PANEL_2.8V
PANEL_13.5V
MT_5V(BL_REG)
REG_GND
VD_SO
VD_SI
VD_SCK
XCS_LCD
PANEL_REVERSE
MT_5V(BL_REG)
VD_SCK
XCS_LCD
VD_SI
VD_SO
BL_ON/OFF
CHASSIS_GND
REG_GND
DISPLAY
BACKLIGHT_SW
REG_GND
TP_Y
MT_5V(BL_REG)
PANEL_2.8V
BL_CONT
TP_SEL1
PANEL_13.5V
REG_GND
REG_GND
REG_GND
REG_GND
REG_GND
TP_X
REG_GND
REG_GND
REG_GND
REG_GND
SP-
LI_3V
PANEL_OPEN_SW
SP+
N.C.
N.C.
CHASSIS_GND
IC2901
3.1V REG
MEMORY
STICK
DUO
LN7403-7408
FLEXIBLE
FP-734
FP-733
FLEXIBLE
LN7301-7329
FP-720 FLEXIBLE
THROUGH THE
(17/18)
CN109
VC-333
SWITCH
BLOCK
CONTROL
MS-153 BOARD
37
05
XX MARK:NO MOUNT
4
C
1189
I
MS CONNECTOR
F
E
2
B
10
D
56 12
H
G
PB
REC
Y/CHROMA
SIGNAL PATH
VIDEO SIGNAL
CHROMA
11
12
(CF4720)
SIGNAL
AUDIO
KEY_AD_0
BL_-V
PAGE 4-59
of LEVEL2
PAGE 4-43
of LEVEL3
PAGE 4-58
of LEVEL2
PAGE 4-58
of LEVEL2
4-51 4-52
MS-153
4-2. SCHEMATIC DIAGRAMS MS-153 BOARD
4-2. SCHEMATIC DIAGRAMS MS-153 BOARD
For Schematic Diagram
• Refer to page 4-75 for printed wiring board.