ST7735R
V0.2 113 2009-08-05
10.1.27 MADCTL (36h): Memory Data Access Control
36H MADCTL (Memory Data Access Control)
Inst / Para D/CX
WRX
RDX
D17-8
D7 D6 D5 D4 D3 D2 D1 D0 HEX
MADCTL 0 ↑ 1 - 0 0 1 1 0 1 1 0 (36h)
Parameter 1 ↑ 1 - MY MX MV ML RGB
MH - -
Description
-This command defines read/ write scanning direction of frame memory.
-Bit Assignment
Send first
Send 2nd
Send 3rd
Send last
Memory Display
Top-left (0, 0)
ML="0"
Send first
Send 2nd
Send 3rd
Send last
Memory Display
Top-left (0, 0)
ML="1"
Top-left (0, 0)
Top-left (0, 0)
R G B R G B R G B
SIG1 SIG2 SIG132
Driver IC
RGB="0"
R G B R G B R G B
SIG1 SIG2 SIG132
Driver IC
RGB="1"
R G B
R G B
SIG1
R G B
R G B
SIG2
R G B
R G B
SIG132
RGB
RGB
SIG1
RGB
RGB
SIG2
RGB
RGB
SIG132
LCD panel LCD panel
Bit NAME DESCRIPTION
MY Row Address Order
MX Column Address Order
MV Row/Column Exchange
These 3bits controls MCU to memory
write/read direction.
ML Vertical Refresh Order
LCD vertical refresh direction control
‘0’ = LCD vertical refresh Top to Bottom
‘1’ = LCD vertical refresh Bottom to Top
RGB RGB-BGR ORDER
Color selector switch control
‘0’ =RGB color filter panel,
‘1’ =BGR color filter panel)
MH Horizontal Refresh Order
LCD horizontal refresh direction control
‘0’ = LCD horizontal refresh Left to right
‘1’ = LCD horizontal refresh right to left
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