ST ST7735R - User Manual

ST
ST7735R
262K Color Single-Chip TFT Controller/Driver
V0.2 1 2009-8-5
1 Introduction
The ST7735R is a single-chip controller/driver for 262K-color, graphic type TFT-LCD. It consists of 396 source line and 162
gate line driving circuits. This chip is capable of connecting directly to an external microprocessor, and accepts Serial
Peripheral Interface (SPI), 8-bit/9-bit/16-bit/18-bit parallel interface. Display data can be stored in the on-chip display data
RAM of 132 x 162 x 18 bits. It can perform display data RAM read/write operation with no external operation clock to
minimize power consumption. In addition, because of the integrated power supply circuits necessary to drive liquid crystal,
it is possible to make a display system with fewer components.
2 Features
Single chip TFT-LCD Controller/Driver with RAM
On-chip Display Data RAM (i.e. Frame Memory)
132 (H) x RGB x 162 (V) bits
LCD Driver Output Circuits:
Source Outputs: 132 RGB channels
Gate Outputs: 162 channels
Common electrode output
Display Colors (Color Mode)
Full Color: 262K, RGB=(666) max., Idle Mode OFF
Color Reduce: 8-color, RGB=(111), Idle Mode ON
Programmable Pixel Color Format (Color Depth) for
Various Display Data input Format
12-bit/pixel: RGB=(444) using the 384k-bit frame memory
and LUT
16-bit/pixel: RGB=(565) using the 384k-bit frame memory
and LUT
18-bit/pixel: RGB=(666) using the 384k-bit frame memory
and LUT
Various Interfaces
Parallel 8080-series MCU Interface
(8-bit, 9-bit, 16-bit & 18-bit)
Parallel 6800-series MCU Interface
(8-bit, 9-bit, 16-bit & 18-bit)
3-line serial interface
4-line serial interface
Display Features
Support both normal-black & normal-white LC
Software programmable color depth mode
Built-in Circuits
DC/DC converter
Adjustable VCOM generation
Non-volatile (NV) memory to store initial register setting
Oscillator for display clock generation
Factory default value (module ID, module version, etc) are
stored in NV memory
Timing controller
Built-in NV Memory for LCD Initial Register Setting
7-bits for ID2
8-bits for ID3
7-bits for VCOM adjustment
Wide Supply Voltage Range
I/O Voltage (VDDI to DGND): 1.65V~3.7V (VDDI ≤ VDD)
Analog Voltage (VDD to AGND): 2.3V~4.8V
On-Chip Power System
Source Voltage (GVDD to AGND): 3.0V~4.5V
VCOM level (VCOM to AGND): -0.4V to -2.0V
Gate driver HIGH level (VGH to AGND): +10.0V to +15V
Gate driver LOW level (VGL to AGND): -13V to -7.5V
Operating Temperature: -30°C to +85°C
ST7735R
Parallel Interface: 8080,6800(8-bit/9-bit/16-bit/18-bit)
Serial Interface: 3-line, 4-line
Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice.

ST ST7735R Specifications

General

Brand	ST
Model	ST7735R
Category	Controller
Language	English

Summary

1 Introduction

2 Features

Key features of the ST7735R controller/driver including RAM, output circuits, colors, interfaces, and integrated systems.

3 Pad arrangement

3.1 Output Bump Dimension

Specifies the dimensions of the output bumps.

3.2 Input Bump Dimension

3.3 Alignment Mark Dimension

3.4 Chip Information

4 Pad Center Coordinates

Coordinates for various PAD names

Lists X and Y coordinates for each PAD name.

5 Block diagram

6 Driver IC Pin Description

6.1 Power Supply Pin

Description of power supply pins (VDD, VDDI, AGND, DGND).

6.2 Interface logic pin

Description of interface logic pins (P68, IM2, IM1, IM0, SPI4W, etc.).

6.3 Mode selection pin

6.4 Driver output pins

6.5 Test pins

7 Driver electrical characteristics

7.1 Absolute operation range

Specifies the absolute maximum and recommended operating ranges for key parameters.

7.2 DC characteristic

7.3 Power consumption

8 Timing chart

8.1 Parallel interface characteristics: 18, 16, 9 or 8-bit bus (8080 series MCU interface)

Timing characteristics for 8080-series parallel interface.

8.2 Parallel interface characteristics: 18, 16, 9 or 8-bit bus (6800 series MCU interface)

8.3 Serial interface characteristics (3-line serial)

8.4 Serial interface characteristics (4-line serial)

9 Function description

9.1 Interface type selection

Explains how IM2, IM1, IM0 pins select MCU interface type.

9.2 8080-series MCU parallel interface (P68 = 0)

9.2.1 Write cycle sequence

9.2.2 Read cycle sequence

9.3 6800-series MCU parallel interface (P68 = 1)

9.3.1 Write cycle sequence

9.3.2 Read cycle sequence

9.4 Serial interface

9.4.1 Command Write Mode

Explains the write mode for serial interfaces (3-line and 4-line).

9.4.2 Read Functions

9.4.3 3-line serial protocol

9.4.4 4-line serial protocol

9.5 Data Transfer Break and Recovery

9.6 Data transfer pause

9.6.1 Serial interface pause

Describes how to pause data transmission over the serial interface.

9.6.2 Parallel interface pause

Describes how to pause data transmission over the parallel interface.

9.7 Data Transfer Modes

9.7.1 Method 1

Describes the first method for transferring data to the display RAM.

9.7.2 Method 2

Describes the second method for transferring data to the display RAM.

9.8 Data Color Coding

9.8.1 8-bit Parallel Interface (IM2, IM1, IM0= 100)

Details color formats for 4k, 65k, and 262k colors in 8-bit parallel.

9.8.2 8-bit data bus for 12-bitpixel (RGB 4-4-4-bit input), 4 K-Colors, 3 AH= 03 h

Explains 8-bit data bus for 12-bit/pixel color depth.

9.8.3 8-bit data bus for 16-bitpixel (RGB 5-6-5-bit input), 65 K-Colors, 3 AH= 05 h

9.8.4 8-bit data bus for 18-bitpixel (RGB 6-6-6-bit input), 262 K-Colors, 3 AH= 06 h

9.8.5 16-Bit Parallel Interface (IM2,IM1, IM0= 101)

9.8.6 16-bit data bus for 12-bitpixel (RGB 4-4-4-bit input), 4 K-Colors, 3 AH= 03 h

9.8.7 16-bit data bus for 16-bitpixel (RGB 5-6-5-bit input), 65 K-Colors, 3 AH= 05 h

9.8.8 16-bit data bus for 18-bitpixel (RGB 6-6-6-bit input), 262 K-Colors, 3 AH= 06 h

9.8.9 9-Bit Parallel Interface (IM2, IM1, IM0=110)

9.8.10 Write 9-bit data for RGB 6-6-6-bit input (262 k-color)

9.8.11 18-Bit Parallel Interface (IM2, IM1, IM0=111)

9.8.12 18-bit data bus for 12-bitpixel (RGB 4-4-4-bit input), 4 K-Colors, 3 AH=03 h

9.8.13 18-bit data bus for 16-bitpixel (RGB 5-6-5-bit input), 65 K-Colors, 3 AH= 05 h

9.8.14 18-bit data bus for 18-bitpixel (RGB 6-6-6-bit input), 262 K-Colors, 3 AH= 06 h

9.8.15 3-line serial Interface

9.8.16 Write data for 12-bitpixel (RGB 4-4-4-bit input), 4 K-Colors, 3 AH= 03 h

9.8.17 Write data for 16-bitpixel (RGB 5-6-5-bit input), 65 K-Colors, 3 AH= 05 h

9.8.18 Write data for 18-bitpixel (RGB 6-6-6-bit input), 262 K-Colors, 3 AH= 06 h

9.8.19 4-line serial Interface

9.8.20 Write data for 12-bitpixel (RGB 4-4-4-bit input), 4 K-Colors, 3 AH= 03 h

9.8.21 Write data for 16-bitpixel (RGB 5-6-5-bit input), 65 K-Colors, 3 AH= 05 h

9.8.22 Write data for 18-bitpixel (RGB 6-6-6-bit input), 262 K-Colors, 3 AH= 06 h

9.9 Display Data RAM

9.9.1 Configuration (GM[1:0] = 00)

Describes the configuration for the display data RAM.

9.9.2 Memory to Display Address Mapping

9.9.3 When using 128 RGB x 160 resolution (GM[1:0] = 11, SMX=SMY=SRGB= 0)

Explains memory to display address mapping for 128x160 resolution.

9.9.4 When using 132 RGB x 162 resolution (GM[1:0] = 00, SMX=SMY=SRGB= 0)

9.9.5 Normal Display On or Partial Mode On

9.9.6 When using 128 RGB x 160 resolution (GM[1:0] = 11)

Describes normal/partial display modes for 128x160 resolution.

9.9.7 When using 132 RGB x 162 resolution (GM[1:0] = 00)

9.10 Address Counter

9.11 Memory Data Write Read Direction

9.11.1 When 128 RGBx160 (GM= 11)

Details write/read direction for 128x160 resolution based on MADCTL parameters.

9.11.2 When 132 RGBx162 (GM= 00)

Details write/read direction for 132x162 resolution based on MADCTL parameters.

9.11.3 Frame Data Write Direction According to the MADCTL parameters (MV, MX and MY)

9.12 Tearing Effect Output Line

9.12.1 Tearing Effect Line Modes

Describes the two modes for the Tearing Effect signal.

9.12.2 Tearing Effect Line Timings

9.12.3 Example 1: MPU Write is faster than panel read

9.12.4 Example 2: MPU write is slower than panel read

9.13 Power ONOFF Sequence

9.13.1 Uncontrolled Power Off

Describes the behavior and consequences of uncontrolled power-off.

9.14 Power Level Definition

9.14.1 Power Level

Defines the six power level modes from maximum to minimum consumption.

9.14.2 Power Flow Chart

9.15 Reset Table (Default Value, GM[1:0]=11, 128 RGB x 160)

9.15.2 Reset Table (GM[1:0]= 00, 132 RGB x 162)

9.16 Module InputOutput Pins

9.16.1 Output or Bi-directional (IO) Pins

Details the behavior of output/bi-directional pins during different states.

9.17 Reset Timing

9.18 Color Depth Conversion Look Up Tables

9.18.1 65536 Color to 262,144 Color

Provides lookup tables for converting 65K colors to 262K colors.

9.18.2 4096 Color to 262,144 Color

10 Command

10.1 System function Command List and Description

Lists and describes system function commands (NOP, SWRESET, RDDID, RDDST, etc.).

10.1.1 NOP (00 h)

10.1.2 SWRESET (01 h): Software Reset

10.1.3 RDDID (04 h): Read Display ID

10.1.4 RDDST (09 h): Read Display Status

10.1.5 RDDPM (0 Ah): Read Display Power Mode

10.1.6 RDDMADCTL (0 Bh): Read Display MADCTL

10.1.7 RDDCOLMOD (0 Ch): Read Display Pixel Format

10.1.8 RDDIM (0 Dh): Read Display Image Mode

10.1.9 RDDSM (0 Eh): Read Display Signal Mode

10.1.10 SLPIN (10 h): Sleep In

10.1.11 SLPOUT (11 h): Sleep Out

10.1.12 PTLON (12 h): Partial Display Mode On

10.1.13 NORON (13 h): Normal Display Mode On

10.1.14 INVOFF (20 h): Display Inversion Off

10.1.15 INVON (21 h): Display Inversion On

10.1.16 GAMSET (26 h): Gamma Set

10.1.17 DISPOFF (28 h): Display Off

10.1.18 DISPON (29 h): Display On

10.1.19 CASET (2 Ah): Column Address Set

10.1.20 RASET (2 Bh): Row Address Set

10.1.21 RAMWR (2 Ch): Memory Write

10.1.22 RGBSET (2 Dh): Color Setting for 4 K, 65 K and 262 K

10.1.23 RAMRD (2 Eh): Memory Read

10.1.24 PTLAR (30 h): Partial Area

10.1.25 TEOFF (34 h): Tearing Effect Line OFF

10.1.26 TEON (35 h): Tearing Effect Line ON

10.1.27 MADCTL (36 h): Memory Data Access Control

10.1.28 IDMOFF (38 h): Idle Mode Off

10.1.29 IDMON (39 h): Idle Mode On

10.1.30 COLMOD (3 Ah): Interface Pixel Format

10.1.31 RDID1 (DAh): Read ID1 Value

10.1.32 RDID2 (DBh): Read ID2 Value

10.1.33 RDID3 (DCh): Read ID3 Value

10.2 Panel Function Command List and Description

10.2.1 FRMCTR1 (B1 h): Frame Rate Control (In normal mode Full colors)

Sets frame frequency for normal mode/full colors.

10.2.2 FRMCTR2 (B2 h): Frame Rate Control (In Idle mode 8-colors)

10.2.3 FRMCTR3 (B3 h): Frame Rate Control (In Partial mode full colors)

10.2.4 INVCTR (B4 h): Display Inversion Control

10.2.5 PWCTR1 (C0 h): Power Control 1

10.2.6 PWCTR2 (C1 h): Power Control 2

10.2.7 PWCTR3 (C2 h): Power Control 3 (in Normal mode Full colors)

10.2.8 PWCTR4 (C3 h): Power Control 4 (in Idle mode 8-colors)

10.2.9 PWCTR5 (C4 h): Power Control 5 (in Partial mode full-colors)

10.2.10 VMCTR1 (C5 h): VCOM Control 1

10.2.11 VMOFCTR (C7 h): VCOM Offset Control

10.2.12 WRID2 (D1 h): Write ID2 Value

10.2.13 WRID3 (D2 h): Write ID3 Value

10.2.14 NVFCTR1 (D9 h): NVM Control Status

10.2.15 NVFCTR2 (DEh): NVM Read Command

10.2.16 NVFCTR3 (DFh): NVM Write Command

10.2.17 GMCTRP1 (E0 h): Gamma (+polarity) Correction Characteristics Setting

10.2.18 GMCTRN1 (E1 h): Gamma (-polarity) Correction Characteristics Setting

11 Power Structure

11.1 Driver IC Operating Voltage Specification

Specifies the operating voltage levels for the driver IC.

11.2 Power Booster Circuit

11.2.1 EXTERNAL COMPONENTS CONNECTION

12 Gamma structure

12.1 TRUCTURE OF GRAYSCALE AMPLIFIER

Explains the grayscale amplifier structure generating 64 voltage levels.

12.2 Gamma Voltage Formula (Positive Negative Polarity)

Provides voltage formulas for positive and negative gamma polarity.

13 Example Connection with Panel direction and Different Resolution

13.1 Application of connection with panel direction

Shows connection examples based on panel direction and pixel order.

13.2 Application of connection with Different resolution

13.3 Microprocessor Interface applications

13.3.1 8080-Series MCU Interface for 8-bit data bus (P68=0, IM2, IM1, IM0=100)

Shows 8080 interface connection for 8-bit data bus.

13.3.2 8080-Series MCU Interface for 16-bit data bus (P68=0, IM2, IM1, IM0=101)

Shows 8080 interface connection for 16-bit data bus.

13.3.3 8080-Series MCU Interface for 9-bit data bus (P68=0, IM2, IM1, IM0=110)

Shows 8080 interface connection for 9-bit data bus.

13.3.4 8080-Series MCU Interface for 18-bit data bus (P68=0, IM2, IM1, IM0=111)

13.3.5 6800-Series MCU Interface for 8-bit data bus (P68=1, IM2, IM1, IM0=100)

13.3.6 6800-Series MCU Interface for 16-bit data bus (P68=1, IM2, IM1, IM0=101)

13.3.7 6800-Series MCU Interface for 9-bit data bus (P68=1, IM2, IM1, IM0=110)

13.3.8 6800-Series MCU Interface for 18-bit data bus (P68=1, IM2, IM1, IM0=111)

13.3.9 3-Line serial MCU Interface (IM2, IM1, IM0=000, SPI4 W=0)

13.3.10 4-Line serial MCU Interface (IM2, IM1, IM0=000, SPI4 W=1)

14 Revision History