ST ST7735R - 9.2.1 Write cycle sequence

ST7735R
V0.2 28 2009-08-05
9.2.1 Write cycle sequence
The write cycle means that the host writes information (command or/and data) to the display via the interface. Each write
cycle (WRX high-low-high sequence) consists of 3 control signals (D/CX, RDX, WRX) and data signals (D[17:0]). D/CX bit
is a control signal, which tells if the data is a command or a data. The data signals are the command if the control signal is
low (=’0’) and vice versa it is data (=’1’).
WRX
D[17:0]
The host starts to control D[17:0]
lines when there is a falling edge
of the WRX.
The display writes D[17:0] lines
when there is a rising edge of
WRX.
The host stops to
control D[17:0] lines.
Figure 9.2.1 8080-series WRX protocol
Note: WRX is an unsynchronized signal (It can be stopped).
CMD CMD PA1 CMD PA
1
PA
N-2
PA
N-1
S P
CMD CMD PA1 CMD PA
1
PA
N-2
PA
N-1
S P
CMD CMD PA1 CMD PA
1
PA
N-2
PA
N-1
S P
D[17:0]
RESX
CSX
D/CX
RDX
WRX
D[17:0]
Host D[17:0]
Host to LCD
Driver D[17:0]
LCD to Host
“1”
“1”
Hi-Z
1-byte
command
2-byte
command
N-byte
command
CMD: write command code
PA: parameter or display data
Signals on D[17:0], D/CX, R/WX, E
pins during CSX=1 are ignored.
Figure 9.2.2 8080-series parallel bus protocol, write to register or display RAM