ST ST7735R - 8.2 Parallel interface characteristics: 18, 16, 9 or 8-bit bus (6800 series MCU interface)

ST7735R
V0.2 23 2009-08-05
8.2 Parallel interface characteristics: 18, 16, 9 or 8-bit bus (6800 series MCU interface)
Figure 8.2.1Parallel interface timing characteristics (6800-series MCU interface)
Ta=25 ℃, VDDI=1.65~3.7V, VDD=2.3~4.8V
Signal Symbol Parameter Min Max Unit Description
T
AST
Address setup time 10 ns
D/CX
T
AHT
Address hold time (Write/Read) 10 ns
-
T
CHW
Chip select “H” pulse width 0 ns
T
CS
Chip select setup time (Write) 15 ns
T
RCS
Chip select setup time (Read ID) 45 ns
T
RCSFM
Chip select setup time (Read FM) 355 ns
T
CSF
Chip select wait time (Write/Read) 10 ns
CSX
T
CSH
Chip select hold time 10 ns
-
T
WC
Write cycle 66 ns
T
WRH
Control pulse “H” duration 15 ns
WRX
T
WRL
Control pulse “L” duration 15 ns
T
RC
Read cycle (ID) 160 ns
T
RDH
Control pulse “H” duration (ID) 90 ns
RDX (ID)
T
RDL
Control pulse “L” duration (ID) 45 ns
When read ID data
T
RCFM
Read cycle (FM) 450 ns
T
RDHFM
Control pulse “H” duration (FM) 90 ns
RDX (FM)
T
RDLFM
Control pulse “L” duration (FM) 355 ns
When read from frame
memory
T
DST
Data setup time 10 ns
T
DHT
Data hold time 10 ns
D[17:0]
T
ODH
Output disable time 20 80 ns
For maximum CL=30pF
For minimum CL=8pF
Table 8.2.1 6800 parallel Interface Characteristics
Note: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30%
and 70% of VDDI for Input signals.