DocID023833 Rev 5 13/36
STM32F42xx and STM32F43xx STM32F42xx and STM32F43xx silicon limitations
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2.1.8 Over-drive and Under-drive modes unavailability
Description
The Over-drive and Under-drive modes are not available on revision A devices.
Workaround
None.
This limitation is fixed in silicon revision Y.
2.2 IWDG peripheral limitation
2.2.1 RVU and PVU flags are not reset in STOP mode
Description
The RVU and PVU flags of the IWDG_SR register are set by hardware after a write access
to the IWDG_RLR and the IWDG_PR registers, respectively. If the Stop mode is entered
immediately after the write access, the RVU and PVU flags are not reset by hardware.
Before performing a second write operation to the IWDG_RLR or the IWDG_PR register,
the application software must wait for the RVU or PVU flag to be reset. However, since the
RVU/PVU bit is not reset after exiting the Stop mode, the software goes into an infinite loop
and the independent watchdog (IWDG) generates a reset after the programmed timeout
period.
Workaround
Wait until the RVU or PVU flag of the IWDG_SR register is reset before entering the Stop
mode.
2.3 I2C peripheral limitations
2.3.1 SMBus standard not fully supported
Description
The I
2
C peripheral is not fully compliant with the SMBus v2.0 standard since It does not
support the capability to NACK an invalid byte/command.
Workarounds
A higher-level mechanism should be used to verify that a write operation is being performed
correctly at the target device, such as:
1. Using the SMBAL pin if supported by the host
2. the alert response address (ARA) protocol
3. the Host notify protocol
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