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STMicroelectronics STM32F429 User Manual
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DocID023833 Rev 5
33/36
STM32F42xx and STM32F
43xx
Revision code on dev
i
ce marking
35
Figure 6. LQFP144 top p
ackage view
!DDITIONALINFORMATIONFIELD
INCLUDING2EVISIONCODE
AIB
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9
EAR
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32
34
Table of Contents
Default Chapter
1
Table 1. Device Identification
1
Table 2. Device Summary
1
Table of Contents
2
ARM 32-Bit Cortex-M4 with FPU Limitations
7
Cortex-M4 Interrupted Loads to Stack Pointer Can Cause
7
Erroneous Behavior
7
Table 3. Cortex-M4 Core Limitations and Impact on Microcontroller Behavior
7
Stm32F42Xx and Stm32F43Xx Silicon Limitations
8
Table 4. Summary of Silicon Limitations
8
System Limitations
10
Debugging Stop Mode and System Tick Timer
10
Debugging Stop Mode with WFE Entry
10
Wakeup Sequence from Standby Mode When Using more than
11
One Wakeup Source
11
Full JTAG Configuration Without NJTRST Pin Cannot be Used
11
MPU Attribute to RTC and IWDG Registers Could be Managed
12
Incorrectly
12
Delay after an RCC Peripheral Clock Enabling
12
Internal Noise Impacting the ADC Accuracy
12
Over-Drive and Under-Drive Modes Unavailability
13
IWDG Peripheral Limitation
13
RVU and PVU Flags Are Not Reset in STOP Mode
13
I2C Peripheral Limitations
13
Smbus Standard Not Fully Supported
13
Start Cannot be Generated after a Misplaced Stop
14
Mismatch on the "Setup Time for a Repeated Start Condition" Timing Parameter
14
Data Valid Time (T VD;DAT ) Violated Without the OVR Flag Being Set
14
Higher than ((VDD+0.3) / 0.7) V
15
I2S Peripheral Limitation
15
In I2S Slave Mode, WS Level Must be Set by the External Master When Enabling the I2S
15
USART Peripheral Limitations
16
Idle Frame Is Not Detected if Receiver Clock Speed Is Deviated
16
In Full Duplex Mode, the Parity Error (PE) Flag Can be Cleared by Writing to the Data Register
16
Parity Error (PE) Flag Is Not Set When Receiving in Mute Mode Using Address Mark Detection
16
Break Frame Is Transmitted Regardless of Ncts Input Line Status
17
Nrts Signal Abnormally Driven Low after a Protocol Violation
17
OTG_FS Peripheral Limitations
17
Data in Rxfifo Is Overwritten When All Channels Are Disabled
17
Simultaneously
17
OTG Host Blocks the Receive Channel When Receiving in Packets and no
18
Txfifo Is Configured
18
Host Channel-Halted Interrupt Not Generated When the Channel Is
18
Disabled
18
Error in Software-Read OTG_FS_DCFG Register Values
18
Ethernet Peripheral Limitations
19
Incorrect Layer 3 (L3) Checksum Is Inserted in Transmitted Ipv6 Packets Without TCP, UDP or ICMP Payloads
19
The Ethernet MAC Processes Invalid Extension Headers in the Received
19
Ipv6 Frames
19
MAC Stuck in the Idle State on Receiving the Txfifo Flush Command Exactly 1 Clock Cycle after a Transmission Completes
19
Transmit Frame Data Corruption
20
Successive Write Operations to the same Register Might Not be Fully
20
Taken into Account
20
Table 5. Impacted Registers and Bits
20
FMC Peripheral Limitation
23
Dummy Read Cycles Inserted When Reading Synchronous Memories
23
FMC Synchronous Mode and NWAIT Signal Disabled
23
Read Access to a Non-Initialized FMC_SDRAM Bank
23
Corruption of Data Read from the FMC
24
Interruption of CPU Read Burst Access to an End of SDRAM Row
24
FMC NOR/PSRAM Controller: Asynchronous Read Access on Bank 2 to 4
24
Returns Wrong Data When Bank 1 Is in Synchronous Mode
24
(BURSTEN Bit Is Set)
24
FMC Dynamic and Static Banks Switching
25
SDIO Peripheral Limitations
25
SDIO HW Flow Control
25
Wrong CCRCFAIL Status after a Response Without CRC Is Received
25
Data Corruption in SDIO Clock Dephasing (NEGEDGE) Mode
26
CE-ATA Multiple Write Command and Card Busy Signal Management
26
No Underrun Detection with Wrong Data Transmission
26
ADC Peripheral Limitations
27
ADC Sequencer Modification During Conversion
27
DAC Peripheral Limitations
27
DMA Underrun Flag Management
27
Figure 1. TFBGA216 Top Package View
29
Figure 2. WLCSP143 Top Package View
30
Figure 3. LQFP208 Top Package View
30
Figure 4. UFBGA176 Top Package View
31
Figure 5. LQFP176 Top Package View
32
Figure 6. LQFP144 Top Package View
33
Figure 7. LQFP100 Top Package View
34
Table 6. Document Revision History
35
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STMicroelectronics STM32F429 Specifications
General
Brand
STMicroelectronics
Model
STM32F429
Category
Controller
Language
English
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